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MC10EL15D bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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1 / 8 page © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 5 Publication Order Number: MC10EL15/D 1 MC10EL15, MC100EL15 5VECL 1:4 Clock Distribution Chip The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. The 100 series contains temperature compensation. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Multiplexed Clock Input • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V • Internal Input Pulldown Resistors on CLKs, SCLK, SEL, and EN. • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SO−16 D SUFFIX CASE 751B 1 16 MARKING DIAGRAMS* 10EL15G AWLYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G= Pb−Free Package 100EL15G AWLYWW http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ORDERING INFORMATION |
Số phần tương tự - MC10EL15D |
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Mô tả tương tự - MC10EL15D |
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