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MC33065P-H bảng dữ liệu(PDF) 8 Page - ON Semiconductor |
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MC33065P-H bảng dữ liệu(HTML) 8 Page - ON Semiconductor |
8 / 18 page MC34065−H, L http://onsemi.com 8 OPERATING DESCRIPTION The MC34065−H,L series are high performance, fixed frequency, dual channel current mode controllers specifically designed for Off−Line and dc−to−dc converter applications. These devices offer the designer a cost effective solution with minimal external components where independent regulation of two power converters is required. The Representative Block Diagram is shown in Figure 15. Each channel contains a high gain error amplifier, current sensing comparator, pulse width modulator latch, and totem pole output driver. The oscillator, reference regulator, and undervoltage lock−out circuits are common to both channels. Oscillator The unique oscillator configuration employed features precise frequency and duty cycle control. The frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink, generating a symmetrical 50 percent duty cycle waveform at Pin 2. The oscillator peak and valley thresholds are 3.5 V and 1.6 V respectively. The source/sink current magnitude is controlled by resistor RT. For proper operation over temperature it must be in the range of 4.0 kΩ to 16 kΩ as shown in Figure 1. As CT charges and discharges, an internal blanking pulse is generated that alternately drives the center inputs of the upper and lower NOR gates high. This, in conjunction with a precise amount of delay time introduced into each channel, produces well defined non−overlapping output duty cycles. Output 2 is enabled while CT is charging, and Output 1 is enabled during the discharge. Figure 2 shows the Maximum Output Duty Cycle versus Oscillator Frequency. Note that even at 500 kHz, each output is capable of approximately 44% on−time, making this controller suitable for high frequency power conversion applications. In many noise sensitive applications it may be desirable to frequency−lock the converter to an external system clock. This can be accomplished by applying a clock signal as shown in Figure 17. For reliable locking, the free−running oscillator frequency should be set about 10% less than the clock frequency. Referring to the timing diagram shown in Figure 16, the rising edge of the clock signal applied to the Sync input, terminates charging of CT and Drive Output 2 conduction. By tailoring the clock waveform symmetry, accurate duty cycle clamping of either output can be achieved. A circuit method for this, and multi−unit synchronization, is shown in Figure 18. Error Amplifier Each channel contains a fully−compensated Error Amplifier with access to the inverting input and output. The amplifier features a typical dc voltage gain of 100 dB, and a unity gain bandwidth of 1.0 MHz with 71° of phase margin (Figure 5). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input through a resistor divider. The maximum input bias current is −1.0 μA which will cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp output (Pin 5, 12) is provided for external loop compensation. The output voltage is offset by two diode drops (≈1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no pulses appear at the Drive Output (Pin 7, 10) when the error amplifier output is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft−start interval (Figures 20, 21). The minimum allowable Error Amp feedback resistance is limited by the amplifier’s source current (0.5 mA) and the output voltage (VOH) required to reach the comparator’s 1.0 V clamp level with the inverting input at ground. This condition happens during initial system startup or when the sensed output is shorted: Rf(min) ≈ 3.0 (1.0 V) ) 1.4 V 0.5 mA = 8800 Ω Current Sense Comparator and PWM Latch The MC34065 operates as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier output. Thus the error signal controls the peak inductor current on a cycle−by−cycle basis. The Current Sense Comparator−PWM Latch configuration used ensures that only a single pulse appears at the Drive Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting a ground−referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 6, 11) and compared to a level derived from the Error Amp output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 5, 12 where: Ipk = V(Pin 5, 12) − 1.4 V 3 RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is: Ipk(max) = 1.0 V RS |
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