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FIN324CMLX bảng dữ liệu(PDF) 3 Page - Fairchild Semiconductor |
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FIN324CMLX bảng dữ liệu(HTML) 3 Page - Fairchild Semiconductor |
3 / 23 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN324C Rev. 1.0.5 3 Pin Definitions Pin I/O Type # Pins Description of Signals Chip-Level Control Signals M/S IN 1 LV-CMOS Master/Slave Control Input: M/S=1 MASTER, M/S =0 SLAVE /RES IN 1 LV_CMOS RESET signal and power-down signal /RES=0: Resets and powers down all circuitry /RES=1: Device enabled /STBY(SLEW) IN 1 LV-CMOS standby signal or output slew rate signal: M/S=1: /STBY M/S=0: RSLEW /STBY=0: Device powered down RSLEW=1: Fast edge rate RSLEW=0: Slow edge rate PAR/SPI IN 1 LV-CMOS parallel / SPI display interface Tells the SerDes it is interfacing with a sub-display with a SPI interface PAR/SPI=1: Parallel Interface PAR/SPI=0: SPI Interface using STRB0(WCLK0) CKSEL(H) IN 1 LV-CMOS Input: Master clock source select input. When M/S=1: CKSEL (passed in serial stream) CKSEL=1: STRB1(WCLK1) Active CKSEL=0: STRB0(WCLK0) Active When M/S=0: This pin must be tied to VDDP. Parallel Interface Signals Master Functionality (Slave Functionality) DP[17:0] DP[6]({SCLK}) DP[7]({SDAT}) I/O 18 LV-CMOS data I/O. I/O direction controlled by M/S pin and R/W internal state. DP[6] SPI mode SCLK signal pin when PAR/SPI=0 (Slave Only) DP[7] SPI mode SDAT signal pin when PAR/SPI=0(Slave Only) CNTL[5:0] {SCLK}CNTL[5] {SDAT}CNTL[4] I/O 6 LV-CMOS data I/O. I/O direction controlled by M/S pin M/S=1: Inputs M/S=0: Outputs In SPI mode, CNTL[5] is SCLK; CNTL[4] is SDAT for master and slave R/W I/O 1 LV-CMOS data I/O. I/O direction controlled by M/S pin. M/S=1: Input M/S=0: Output Functional operation: R/W=1: Read R/W=0: Write STRB0(WCLK0) I/O 1 LV-CMOS data I/O. Function controlled by M/S pin. M/S=1: STRB0 Input M/S=0: WCLK0 Output STRB1(WCLK1) I/O 1 LV-CMOS Data I/O. Function controlled by M/S pin. M/S=1: STRB1 Input M/S=0: WCLK1 Output |
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