1N6267A Series

http://onsemi.com

5

1N6373, ICTE-5, MPTE-5,

through

1N6389, ICTE-45, C, MPTE-45, C

1.5KE6.8CA

through

1.5KE200CA

Figure 6. Dynamic Impedance

1000

500

200

100

50

20

10

5

2

1

1000

500

200

100

50

20

10

5

2

1

0.3

0.5 0.7

1

2

3

5

7

10

20 30

0.3

0.5 0.7

1

2

3

5

7

10

20 30

20V

24V

43V

75V

180V

120V

20V

24V

43V

Figure 7. Typical Derating Factor for Duty Cycle

1 ms

10 ms

1

0.7

0.5

0.3

0.05

0.1

0.2

0.01

0.02

0.03

0.07

100 ms

0.1

0.2

0.5

2

5

10

50

1

20

100

D, DUTY CYCLE (%)

PULSE WIDTH

10 ms

APPLICATION NOTES

RESPONSE TIME

In most applications, the transient suppressor device is

placed in parallel with the equipment or component to be

protected. In this situation, there is a time delay associated

with the capacitance of the device and an overshoot

condition associated with the inductance of the device and

the inductance of the connection method. The capacitance

effect is of minor importance in the parallel protection

scheme because it only produces a time delay in the

transition from the operating voltage to the clamp voltage as

shown in Figure 8.

The inductive effects in the device are due to actual

turn-on time (time required for the device to go from zero

current to full current) and lead inductance. This inductive

effect produces an overshoot in the voltage across the

equipment or component being protected as shown in

Figure 9. Minimizing this overshoot is very important in the

application, since the main purpose for adding a transient

suppressor is to clamp voltage spikes. These devices have

excellent response time, typically in the picosecond range

and negligible inductance. However, external inductive

effects could produce unacceptable overshoot. Proper

circuit layout, minimum lead lengths and placing the

suppressor device as close as possible to the equipment or

components to be protected will minimize this overshoot.

prevent overstress of the protection device. This impedance

should be as high as possible, without restricting the circuit

operation.

DUTY CYCLE DERATING

The data of Figure 1 applies for non-repetitive conditions

and at a lead temperature of 25

°C. If the duty cycle increases,

the peak power must be reduced as indicated by the curves

of Figure 7. Average power must be derated as the lead or