SN74ABT18502

SCAN TEST DEVICE

WITH 18-BIT REGISTERED BUS TRANSCEIVER

SCBS753 – FEBRUARY 2002

8

POST OFFICE BOX 655303

register overview

With the exception of the bypass register and device IDR, any test register can be thought of as a serial shift

register with a shadow latch on each bit. The bypass register and device IDR differ in that they contain only a

shift register. During the appropriate capture state (Capture-IR for the IR, Capture-DR for DRs), the shift register

may be parallel loaded from a source specified by the current instruction. During the appropriate shift state

(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted

in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from

the shift register.

instruction register (IR)

The IR is eight bits long and is used to tell the device what instruction is to be executed. Information contained

in the instruction includes the mode of operation (either normal mode, in which the device performs its normal

logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be

performed, which of the four DRs is to be selected for inclusion in the scan path during DR scans, and the source

of data to be captured into the selected DR during Capture-DR.

Table 4 lists the instructions supported by the SN74ABT18502. The even-parity feature specified for SCOPE

devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are

defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted

out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value

that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated

and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the

binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TDO

TDI

Bit 7

Parity

(MSB)

Bit 0

(LSB)

Figure 2. IR Order of Scan