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74F283 bảng dữ liệu(PDF) 2 Page - Fairchild Semiconductor |
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74F283 bảng dữ liệu(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Functional Description The 74F283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0). The binary sum appears on the Sum (S0–S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the sub- script numbers, representing powers of two. 20 (A0 + B0 + C0) + 2 1 (A 1 + B1) + 22 (A 2 + B2) + 2 3 (A 3 + B3) = S 0 + 2S1 + 4S2 + 8S3 + 16C4 Where ( +) = plus Interchanging inputs of equal weight does not affect the operation. Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages. Due to the symmetry of the binary add function, the 74F283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure 1. Note that if C0 is not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic. Due to pin limitations, the intermediate carries of the 74F283 are not brought out for use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure 2 shows how to make a 3-bit adder. Tying the oper- and inputs of the fourth adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure 3 shows a way of dividing the 74F283 into a 2-bit and a 1-bit adder. The third stage adder (A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1– I5 that are true. Figure 5 shows one method of implement- ing a 5-input majority gate. When three or more of the inputs I1–I5 are true, the output M5 is true. Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0 FIGURE 1. Active HIGH versus Active LOW Interpretation FIGURE 2. 3-Bit Adder FIGURE 3. 2-Bit and 1-Bit Adders FIGURE 4. 5-Input Encoder FIGURE 5. 5-Input Majority Gate C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4 Logic Levels L L H L H H L L H H H L L H Active HIGH 00 101 100 111 001 Active LOW 1 1 010 011 000 110 |
Số phần tương tự - 74F283_04 |
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Mô tả tương tự - 74F283_04 |
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