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9 / 16 page STD90NH02L- STD90NH02L-1 Appendix A 9/16 4 Appendix A The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. ● The low side (SW2) device requires: ● Very low RDS(on) to reduce conduction losses ● Small Qgls to reduce the gate charge losses ● Small Coss to reduce losses due to output capacitance ● Small Qrr to reduce losses on SW1 during its turn-on ● The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source ● voltage to avoid the cross conduction phenomenon; ● The high side (SW1) device requires: ● Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate ● Small Qg to have a faster commutation and to reduce gate charge losses ● Low RDS(on) to reduce the conduction losses. Figure 19. Buck converter: power losses estimation Table 6. Power losses calculation High side switching (SW1) Low side switch (SW2) Pconduction Pswitching Zero Voltage Switching δ * I * R 2 L DS(on)SW1 ) 1 ( * I * R 2 L DS(on)SW2 δ − g L I I * f * ) Q (Q * V gd(SW1) gsth(SW1) in + |
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