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RECOMMENDED OPERATING CONDITIONS

ADS5231

SBAS295A – JULY 2004 – REVISED JANUARY 2007

ADS5231

MIN

TYP

MAX

UNITS

SUPPLIES AND REFERENCES

Analog Supply Voltage, AVDD

3.0

3.3

3.6

V

Output Driver Supply Voltage, VDRV

3.0

3.3

3.6

V

1.875

2.0

2.05

V

0.95

1.0

1.125

V

V

0.75

1.0

1.1

V

V

CLOCK INPUT AND OUTPUTS

ADCLK Input Sample Rate

PLL Enabled (default)

20

40

MSPS

PLL Disabled

2

MSPS

ADCLK Duty Cycle

PLL Enabled (default)

45

55

MSPS

Low-Level Voltage Clock Input

0.6

V

High-Level Voltage Clock Input

2.2

V

–40

+85

°C

Thermal Characteristics:

θ

JA

42.8

°C/W

θ

JC

18.7

°C/W

(1)

These voltages need to be set to 1.5V

± 50mV if they are derived independent of V

(2)

When the PLL is disabled, the clock duty cycle needs to be controlled well, especially at higher speeds. A 45%–55% duty cycle variation

is acceptable up to a frequency of 30MSPS. If the device needs to be operated in the PLL disabled mode beyond 30MSPS, then the

duty cycle needs to be maintained within 48%–52% duty cycle.

3

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