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ADS5231 bảng dữ liệu(PDF) 7 Page - Burr-Brown (TI) |
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ADS5231 bảng dữ liệu(HTML) 7 Page - Burr-Brown (TI) |
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7 / 26 page  www.ti.com TIMING CHARACTERISTICS (1) ADS5231 SBAS295A – JULY 2004 – REVISED JANUARY 2007 Typical values at T A = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty cycle, and total capacitive loading = 10pF, unless otherwise noted. PARAMETER MIN TYP MAX UNITS 40MSPS With PLL ON tA Aperture Delay 2.1 ns Aperture Jitter 1.0 ps t1 Data Setup Time(2) 3.7 5.5 ns t2 Data Hold Time(3) 11.5 13.5 ns tD Data Latency 6 Clocks tDR, tDF Data Rise/Fall Time(4) 0.5 2 3 ns Data Valid (DV) Duty Cycle 30 40 55 % tDV Input Clock Rising to DV Fall Edge 13.5 16 18.5 ns 30MSPS With PLL OFF tA Aperture Delay 2.1 ns Aperture Jitter 1.0 ps t1 Data Setup Time 8 10 ns t2 Data Hold Time 14 19 ns tD Data Latency 6 Clocks tDR, tDF Data Rise/Fall Time 0.5 2 3.5 ns Data Valid (DV) Duty Cycle 30 45 55 % tDV Input Clock Rising to DV Fall Edge 16 19 21 ns 20MSPS With PLL ON tA Aperture Delay 2.1 ns Aperture Jitter 1.0 ps t1 Data Setup Time 10 12 ns t2 Data Hold Time 20 25 ns tD Data Latency 6 Clocks tDR, tDF Data Rise/Fall Time 0.5 2 3.5 ns Data Valid (DV) Duty Cycle 30 45 55 % tDV Input Clock Rising to DV Fall Edge 20 25 30 ns 20MSPS With PLL OFF tA Aperture Delay 2.1 ns Aperture Jitter 1.0 ps t1 Data Setup Time 10 12 ns t2 Data Hold Time 20 25 ns tD Data Latency 6 Clocks tDR, tDF Data Rise/Fall Time 0.5 2 3.5 ns Data Valid (DV) Duty Cycle 30 45 55 % tDV Input Clock Rising to DV Fall Edge 20 25 30 ns 2MSPS With PLL OFF tA Aperture Delay 2.1 ns Aperture Jitter 1.0 ps t1 Data Setup Time 150 200 ns t2 Data Hold Time 200 250 ns tD Data Latency 6 Clocks tDR, tDF Data Rise/Fall Time 0.5 2 3.5 ns Data Valid (DV) Duty Cycle 30 45 55 % tDV Input Clock Rising to DV Fall Edge 200 225 250 ns (1) Specifications assured by design and characterization; not production tested. (2) Measured from data becoming valid (at a high level = 2.0V and a low level = 0.8V) to the 50% point of the falling edge of DV. (3) Measured from the 50% point of the falling edge of DV to the data becoming invalid. (4) Measured between 20% to 80% of logic levels. 7 Submit Documentation Feedback |
Số phần tương tự - ADS5231 |
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Mô tả tương tự - ADS5231 |
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