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MC141803 bảng dữ liệu(PDF) 10 Page - Motorola, Inc

tên linh kiện MC141803
Giải thích chi tiết về linh kiện  LCD Segment / Common Driver with Controller CMOS
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
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MOTOROLA
3–322
MC141803
D/C (Data / Command)
This input pin let the driver distinguish the input at D0-D7 is data or
command. Input High for data while input Low for command.
CS (CLK) (Chip Select / Input Clock)
This pin is normal Low clock input. Data on D0-D7 is latched at the
falling edge of CS.
RES (Reset)
An active Low pulse to this pin reset the internal status of the
driver (same as power on reset). The minimum pulse width is 10
µs.
CE (Chip Enable)
HIGH input to this pin to enable the control pins on the driver.
D0-D7
This bi-directional bus is used for data / command transferring.
R/W (Read/Write)
This is an input pin. To read the display data RAM or the internal
status (Busy / Idle), pull this pin High. The R/W input Low indicates a
write operation to the display data RAM or to the internal setup regis-
ters.
OSC1 (Oscillator Input)
For internal oscillator mode, this is an input for the internal low
power RC oscillator circuit. In this mode, an external resistor of cer-
tain value is placed between the OSC1 and OSC2 pins for a range of
internal operating frequencies (refer to Figure 1). For external oscilla-
tor mode, OSC1 should be left open.
OSC2 (Oscillator Output / External Oscillator Input)
This is an output for the internal low power RC oscillator circuit.
For external oscillator mode, OSC2 will be an input pin for external
clock and no external resistor is needed.
VLL6 - VLL2
Group of voltage level pins for driving the LCD panel. They can
either be connected to external driving circuit for external bias supply
or connected internally to built-in divider circuit. For internal Voltage
Divider enabled, a 0.1
µF capacitor to AV
SS is required on each pin.
DUM1 and DUM2
If internal Voltage Divider is enabled with 1/7 bias selected, a
capacitor to AVSS is required on each pin. Otherwise, pull these two
pin to AVSS
C1N and C1P
If Internal DC/DC Converter is enabled, a capacitor is required to
connect these two pins.
C2N and C2P
If internal Tripler is enabled, a capacitor is required between these
two pins. Otherwise, leave these pin open.
C+ and C-
If internal divider circuit is enabled, a capacitor is required to con-
nect between these two pins.
VR and VF
This is a feedback path for the gain control (external contrast con-
trol) of VLL1 to VLL6. For adjusting the LCD driving voltage, it
requires a feedback resistor placed between VR and VF, a gain con-
trol resistor placed between VF and AVSS, a 10
µF capacitor placed
between VR and AVSS. (Refer to the Application Circuit)
COM0-COM32 (Row Drivers)
These pins provide the row driving signal to LCD panel. Com0-
Com31 are used in 32 mux configuration. Com0-Com15 are used in
16 mux and no row remap configuration while Com16-Com31 are
used in 16 mux with row remap configuration. Com32 is used to drive
the non-static icons in 33 Mux. They output 0V during display off.
(Note : The IC facilitates two Com32 pins, which output same signal,
for the LCD panel layout flexibility.)
SEG0-SEG119 (Column Drivers)
These 120 pins provide LCD column driving signal to LCD panel.
They output 0V during display off.
BP (Annunciator Backplane)
This pin combines with Annun0-Annun3 pins to form annunciator
driving part. When the annunciator circuit is enabled, it will output
square wave of FANNn Hz. It outputs low when oscillator is disabled.
Annun0 - Annun3 (Annunciator Frontplanes)
These pins are four independent annunciator driving outputs. The
enabled annunciator outputs from its corresponding pin a FANNn Hz
square wave which is 180 degrees out of phase with BP. Disabled
annunciator output from its corresponding pin an square wave in-
phase with BP. When oscillator is disabled, all these pins output 0V.
AVDD and AVSS
AVDD is the positive supply to the noise sensitive circuitry in LCD
Driver and should be at same level as DVDD. AVSS is ground.
VCC
For using the Internal DC/DC Converter, a 0.1
µF capacitor from
this pin to AVSS is required. It can also be an external bias input pin
if Internal DC/DC Converter is not used. Positive power is supplied to
the LCD Driving Level Selector and HV Buffer Cell with this pin. Nor-
mally, this pin is not intended to be a power supply to other compo-
nent.
DVDD and DVSS
Power is supplied to the digital control circuit and other circuitry in
LCD bias Voltage Generator of the driver using these two pins.
DVDD is power and DVSS is ground.
PIN DESCRIPTIONS


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