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MCF5251DVM140 bảng dữ liệu(PDF) 6 Page - Freescale Semiconductor, Inc |
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MCF5251DVM140 bảng dữ liệu(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 32 page Signal Description MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 2.1 6 Freescale Semiconductor 3 Signal Description This chapter describes the MCF5251 input and output signals. The signal descriptions as shown in Table 3 are grouped according to relevant functionality. For additional signal information, see “Chapter 2, Signal Description” in the MCF5251 reference manual. UART Universal Asynchronous Receiver /Transmitter Module Connectivity Peripheral Three UARTs handle asynchronous serial communication. USBOTG USB 2.0 High-Speed On-The-Go Connectivity Peripheral The USB module is used for communication to a PC or communication to slave devices; for example, to download data from a hard disc player to a flash player, and to other devices. Table 3. MCF5251 Signal Index Signal Name Mnemonic Function Input/ Output Reset State Address A[24:1] A[23]/GPO54 24 address lines—address 23 is multiplexed with GPO54 and address 24 is multiplexed with A20 (SDRAM access only). Out X Read-write control RW Bus write enable—indicates if read or write cycle in progress. Out H Output enable OE Output enable for asynchronous memories connected to chip selects Out negated Data D[31:16] Data bus used to transfer word data In/Out Hi-Z Synchronous row address strobe SDRAS/GPIO59 Row address strobe for external SDRAM Out negated Synchronous column address strobe SDCAS/GPIO39 Column address strobe for external SDRAM Out negated SDRAM write enable SDWE/GPIO38 Write enable for external SDRAM Out negated SDRAM upper byte enable SDUDQM/GPO53 Upper byte enable—indicates during write cycle if high byte is written. Out – SDRAM lower byte enable SDLDQM/GPO52 Lower byte enable—indicates during write cycle if low byte is written. Out – SDRAM chip selects SD_CS0/GPIO60 SDRAM chip select In/Out negated SDRAM clock enable BCLKE/GPIO63 SDRAM clock enable Out – System clock BCLK/GPIO40 SDRAM clock output In/Out – Table 2. Digital and Analog Modules (continued) Block Mnemonic Block Name Functional Grouping Brief Description |
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Mô tả tương tự - MCF5251DVM140 |
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