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ADS8329IBRSAT bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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ADS8329IBRSAT bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 40 page www.ti.com TIMING CHARACTERISTICS ADS8329 ADS8330 SLAS516 – DECEMBER 2006 All specifications typical at –40°C to 85°C, +VA = 2.7 v, +VBD = 1.8 V (unless otherwise noted) (1)(2) PARAMETER MIN TYP MAX UNIT External, 3 V ≤ +VA ≤ 3.6 V 0.5 21 Frequency, conversion clock, CCLK, fCCLK External, 2.7 V ≤ +VA ≤ 3 V 0.5 18.9 MHz fCCLK = 1/2 fSCLK Internal 21 22.3 23.5 tsu(CSF-EOC) Setup time, falling edge of CS to EOC 1 CCLK th(CSF-EOC) Hold time, falling edge of CS to EOC 0 ns twL(CONVST) Pulse duration, CONVST low 40 ns tsu(CSF-EOS) Setup time, falling edge of CS to EOS 20 ns th(CSF-EOS) Hold time, falling edge of CS to EOS 20 ns tsu(CSR-EOS) Setup time, rising edge of CS to EOS 20 ns th(CSR-EOS) Hold time, rising edge of CS to EOS 20 ns tsu(CSF-SCLK1R) Setup time, falling edge of CS to SCLK 5 tc(SCLK) - 5 ns twL(SCLK) Pulse duration, SCLK low 8 tc(SCLK) - 8 ns twH(SCLK) Pulse duration, SCLK high 8 tc(SCLK) - 8 ns I/O Clock only 23.8 I/O and conversion clock, 23.8 2000 3 V ≤ +VA ≤ 3.6 V I/O and conversion clock, 26.5 2000 2.7 V ≤ +VA < 3 V I/O Clock, chain mode 23.8 tc(SCLK) Cycle time, SCLK ns I/O and conversion clock, chain mode, 23.8 2000 3 V ≤ +VA ≤ 3.6 V I/O and conversion clock, chain mode, 26.5 2000 2.7 V ≤ +VA < 3 V Delay time, falling edge of SCLK to SDO td(SCLKF-SDOINVALID) 10-pF Load 8 ns invalid Delay time, falling edge of SCLK to SDO td(SCLKF-SDOVALID) 10-pF Load 23 ns valid Delay time, falling edge of CS to SDO td(CSF-SDOVALID) 10-pF Load 23 ns valid, SDO MSB output tsu(SDI-SCLKF) Setup time, SDI to falling edge of SCLK 8 ns th(SDI-SCLKF) Hold time, SDI to falling edge of SCLK 4 ns Delay time, rising edge of CS/FS to SDO td(CSR-SDOZ) 8 ns 3-state Setup time, last falling edge of SCLK tsu(lastSCLKF-CSR) 10 ns before rising edge of CS/FS Delay time, CDI high to SDO high in td(SDO-CDI) 10-pF Load, chain mode 23 ns daisy chain mode (1) All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. 8 Submit Documentation Feedback |
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