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AD9985AKSTZ-140 bảng dữ liệu(PDF) 11 Page - Analog Devices |
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AD9985AKSTZ-140 bảng dữ liệu(HTML) 11 Page - Analog Devices |
11 / 32 page AD9985A Rev. 0 | Page 11 of 32 DESIGN GUIDE GENERAL DESCRIPTION The AD9985A is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel moni- tors or projectors. The circuit is ideal for providing a computer interface for HDTV monitors or as the front end to high performance video scan converters. Implemented in a high performance CMOS process, the interface can capture signals with pixel rates up to 110 MHz. The AD9985A includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. All controls are programmable via a 2-wire serial interface. Full integration of these sensitive analog functions makes system design straightforward and less sensitive to the physical and electrical environment. With a typical power dissipation of only 500 mW and an operating temperature range of 0°C to 70°C (−40°C to +85°C for the AD9985ABST), the device requires no special environmental considerations. DIGITAL INPUTS All digital inputs on the AD9985A operate to 3.3 V CMOS levels. However, all digital inputs are 5 V tolerant. Applying 5 V to them does not cause any damage. INPUT SIGNAL HANDLING The AD9985A has one high impedance analog input pin for each of the red, green, and blue channels. They accommodate signals ranging from 0.5 V to 1.0 V p-p. Signals are typically brought onto the interface board via a DVI-I connector, a 15-pin D connector, or via BNC connectors. The AD9985A should be located as close as practical to the input connector. Signals should be routed via matched- impedance traces (normally 75 Ω) to the IC input pins. At this point, the signal should be resistively terminated (75 Ω to the signal ground return) and capacitively coupled to the AD9985A inputs through 47 nF capacitors. These capacitors form part of the dc restoration circuit. When impedances are perfectly matched, the best performance can be obtained with the widest possible signal bandwidth. The ultrawide bandwidth inputs of the AD9985A (300 MHz) can track the input signal continuously as it moves from one pixel level to the next, and digitize the pixel during a long, flat pixel time. In many systems, however, there are mismatches, reflections, and noise, which can result in excessive ringing and distortion of the input waveform. This makes it more difficult to establish a sampling phase that provides good image quality. It has been shown that a small inductor in series with the input is effective in rolling off the input bandwidth slightly and providing a high quality signal over a wider range of conditions. Using a Fair-Rite #2508051217Z0 High Speed Signal Chip Bead inductor in the circuit of Figure 3 yields good results in most applications. RGB INPUT RIN GIN BIN 47nF 75 Ω Figure 3. Analog Input Interface Circuit HSYNC, VSYNC INPUTS The interface also takes a horizontal sync signal, which is used to generate the pixel clock and clamp timing. This can be either a sync signal directly from the graphics source, or a preproc- essed TTL or CMOS level signal. The Hsync input includes a Schmitt trigger buffer for immunity to noise and signals with long rise times. In typical PC-based graphic systems, the sync signals are simply TTL-level drivers feeding unshielded wires in the monitor cable. As such, no termination is required. SERIAL CONTROL PORT The serial control port is designed for 3.3 V logic. If there are 5 V drivers on the bus, these pins should be protected with 150 Ω series resistors placed between the pull-up resistors and the input pins. OUTPUT SIGNAL HANDLING The digital outputs are designed and specified to operate from a 3.3 V power supply (VDD). They can also work with a VDD as low as 2.5 V for compatibility with other 2.5 V logic. CLAMPING RGB Clamping To properly digitize the incoming signal, the dc offset of the input must be adjusted to fit the range of the on-board ADCs. Most graphics systems produce RGB signals with black at ground and white at approximately 0.75 V. However, if sync signals are embedded in the graphics, the sync tip is often at ground, black is at 300 mV, and white is at approximately 1.0 V. Some common RGB line amplifier boxes use emitter-follower buffers to split signals and increase drive capability. This introduces a 700 mV dc offset to the signal, which must be removed for proper capture by the AD9985A. The key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. An offset is then introduced that results in the ADCs producing a |
Số phần tương tự - AD9985AKSTZ-140 |
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Mô tả tương tự - AD9985AKSTZ-140 |
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