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MYSON
TECHNOLOGY
MTV212M32
(Rev 1.1)
Revision 1.1
- 6 -
2000/07/04
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTV212M32 includes all 8051 functions with the following exceptions:
1.1 The external RAM access is restricted to XFRs/AUXRAM within the MTV212M32.
1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor
special application.
1.3 INT1 input pin is not provided, it is connected to special interrupt sources.
1.4 Port2 are shared with special function pins.
In addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051.
Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map
please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV212M32, same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are
used for monitor control or PWM DAC. Program can initialize Ri value and use "MOVX" instruction to access
these registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 256 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The AUXRAM is
divided into two banks, selected by XBANK register. Program can initialize Ri value and use "MOVX"
instruction to access the AUXRAM.
00h
7Fh
80h
FFh
AUXRAM
Accessible by
indirect external
RAM addressing
(XBANK=0)(Using
MOVX A,@Ri
instruction)
XFR
Accessible by
indirect external
RAM addressing
(Using
MOVX A,@Ri
instruction
AUXRAM
Accessible by
indirect external
RAM addressing
(XBANK=1)(Using
MOVX A,@Ri
instruction)
00h
7Fh
80h
FFh
Internal RAM
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
Internal RAM
Accessible by
direct and indirect
addressing
SFR
Accessible by
direct addressing


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