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MC145003FU bảng dữ liệu(PDF) 7 Page - Motorola, Inc

tên linh kiện MC145003FU
Giải thích chi tiết về linh kiện  128 SEGMENT LCD DRIVERS CMOS
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nhà sản xuất  MOTOROLA [Motorola, Inc]
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MC145003
• MC145004
7
MOTOROLA
VDD
Positive Power Supply (Pin 49)
This pin supplies power to the main processor interface and
logic portions of the device. The voltage range is 2.8 to 5.5 V
with respect to the VSS pin.
For optimum performance, VDD should be bypassed to
VSS using a low inductance capacitor mounted very closely to
these pins. Lead length on this capacitor should be minimized.
VSS
Ground (Pin 21)
Common ground.
DATA INPUT PROTOCOL
Two–wire communication bus DCLK, Din; three–wire com-
munication bus DCLK, Din, ENB.
MC145003 — SPI DEVICE (FIGURE 7)
Before communication with an MC145003 can begin, a start
condition must be set up on the bus by the transmitter. To
establish a start condition, the transmitter must pull the data
line low while the clock line is high. The “idle” state for the
clock line and data line is the high state.
After the start condition has been established, an eight–bit
address should be sent by the transmitter. If the address sent
corresponds to the address of (one of) the MC145003(s) then
on each successive clock pulse, the addressed device will
accept a data bit.
If the ENB pin is permanently high, then the addressed
MC145003’s internal counter latches the data to be displayed
after 128 data bits have been received. Otherwise, the control
of this latch function may be overridden by holding the ENB
line low until the new data is required to be displayed, then a
high pulse should be sent on the ENB line. The high pulse
must be sent during DCLK high (clock idle).
To end communication with an MC145003, a stop condition
should be set up on the bus (or another start condition may be
set up if another communication is desired). Note that the
communication channel to an addressed device may be left
open after the 128 data bits have been sent by not setting up
a stop or a start condition. In such a case, the 129th rising
DCLK edge, which normally would be used to set up the stop
or start condition, is ignored by the MC145003 and data con-
tinues to be received on the 130th rising DCLK. The latch func-
tion continues to work as normal (i.e., data is be latched either
after each block of 128 data bits has been received or under
external control as required).
At any time during data transmission, the transfer may be
interrupted with a stop condition. Data transmission may be
resumed with a start condition and resending the address.
Interfacing the MC145003 with the MC6805 family
The MC145003 performs as a slave receiver in an SPI envi-
ronment if the clock idle state has been defined to be “high”
(SPICR5 = 1). In three–wire or four–wire SPI environments,
the slave select wire (SPISS) can be used for the ENB pin on
the MC145003 as described above. Note that in full duplex
SPI environments, MC145003 only receives data, it does not
re–transmit data.
MC145004 — IIC DEVICE (FIGURE 8)
Before communication with an MC145004 can begin, a start
condition must be set up on the bus by the controller. To estab-
lish a start condition, the controller must pull the data line low
while the clock line is high.
After the start condition has been established, an eight–bit
address should be sent by the controller followed by an extra
clock pulse while the data line is left high. In this option, only
the seven most significant bits of the address are used to
uniquely define devices on the bus, the least significant bit is
used as a read/write control: if the least significant bit is 0, then
the controller writes to the LCD driver; if it is 1, then the con-
troller reads from the LCD driver’s 128–bit shift register on a
first–in first–out basis. If the seven most significant address
bits sent correspond to the address of (one of) the LCD driv-
er(s) then the addressed LCD driver responds by sending an
“acknowledge” bit back to the controller (i.e., the LCD driver
pulls the data line low during the extra clock pulse supplied by
the controller). If the least significant address bit was 0, then
the controller should continue to send data to the LCD driver
in blocks of eight bits followed by an extra ninth clock pulse to
allow the LCD driver to pull the data line Din low as an acknowl-
edgement. If the least significant address bit was 1, then the
LCD driver sends data back to the controller (the clock is sup-
plied by the controller). After each successive group of eight
bits sent, the LCD driver leaves the data line high for one
pulse.
If the ENB pin is permanently high, then the addressed
MC145004’s internal counter latches the data to be displayed
after 128 data bits have been received. Otherwise the control
of this latch function may be overridden by holding the ENB
line low until the new data is required to be displayed, then a
high pulse should be sent on the ENB line. The high pulse
must be sent during DCLK high (clock idle).
To end communication with an MC145004, a stop condition
should be set up on the bus (or another start condition may be
set up if another communication is desired). Note that the
communication channel to an addressed device may be left
open after the 128 data bits have been sent by not setting up
a stop or a start condition. In such a case the rising DCLK edge
which comes after all 128 data bits have been sent and after
the last acknowledge–related clock pulse has been made is
ignored; data continues to be received on the following DCLK
high. The latch function continues to work as normal (i.e., data
is latched either after each block of 128 data bits has been re-
ceived or under external control as required).
At any time during data transmission, the transfer may be
interrupted with a stop condition. Data transmission may be
resumed with a start condition and resending the address.
CASCADED OPERATION
The master device supplies the oscillator input via its OSC2
pin to the slave devices via their OSC2 pin(s). It sends a frame
sync pulse via its FS pin to the slaves via their FS pins at the
beginning of every BP1 valid time. In Figure 9, the ENB pins
are tied together and used as a chip enable to latch the new
data — the ENB pins could have been tied to VDD if it were de-
sirable to use the internal data bit counter to latch the new
data.
The four backplane inputs may come from the master only,
with the slave backplanes being left open, as shown in Figure
6, or if more drive is required, then the slaves’ backplanes may
be connected to the corresponding backplanes of the master.
Example: at room temperature, with a drive frequency of 30
Hz, around four to five MC145003/MC145004s may be used
in a system where only the master’s backplanes are con-
nected to the LCD. For applications with heavier loads (e.g.,
large liquid crystals) or high drive frequencies or at high tem-
peratures, the dc voltage component seen by the LCD may be
kept to a minimum by connecting the corresponding back-
planes of all participating MC145003/MC145004s together.


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