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MC145003 bảng dữ liệu(PDF) 6 Page - Motorola, Inc |
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MC145003 bảng dữ liệu(HTML) 6 Page - Motorola, Inc |
6 / 14 page MC145003 • MC145004 MOTOROLA 6 PIN DESCRIPTIONS A0–A2 Address Inputs (Pins 42–44) The devices have to receive a correct address before they will accept data. Three address pins (A2, A1, A0) are used to define the states of the three programmable bits of MC145003/MC145004’s 8–bit address. The address is 0111vwxy where v, w, x represent A2, A1, and A0 respectively. Where v, w, x = 0, then A2, A1, and A0 should be tied to 0 V. Where v, w, x = 1, then A2, A1, and A0 should be tied to VDD. For systems where only one MC145003/MC145004 is used, the address pins must be tied to VDD. This defines the device as a master. Other configurations of the address pins (except 000*) defines a device to be a slave. For systems with more than one MC145003/MC145004 (cascaded application) one of the MC145003/MC145004 must have all of its address pins tied to VDD (this defines it as the master). The master is responsible for: 1. Supplying the oscillator input to all slaves. 2. Sending one frame sync pulse at the beginning of every BP1 (backplane 1) period to keep the MC145003/ MC145004 synchronized. 3. Supplying a common set of backplane signals to be shared by all participating devices in the cascaded sys- tem (if desired). NOTE Note: In applications where the circuit will be isolated from external manual interference the system designer may take ad- vantage of the self–programming feature. Upon power–on, ad- dress pins which are left open–circuit will be charged to VDD. However, care must be taken not to inadvertently discharge the pins after power–on since the address may then be lost. A simi- lar feature is also available on the ENB pin. CAUTION The configuration A0, A1, A2 = 000 should not be used. This does not give a valid address and is reserved for Motorola’s use only. All three address pins should never be tied to 0 V simulta- neously. Any other combination of Master (111) plus six Slaves (110, 101, 100, 011, 010, 001) is allowed. ENB Enable Input (Pin 41) If the ENB pin is tied to VDD, the MC145003/MC145004 will always latch the data after 128 bits have been received. The latched data is multiplexed and fed to the frontplane drivers for display. If external control of this latching function is required (for example, in a cascaded application where multiplexing of new data may require a delay until all participating MC145003/MC145004 data is updated), then the ENB pin should be held low, followed by one high pulse on ENB when data display is required. (This may also be useful in a system where one MC145003/MC145004 is permanently addressed and only the last 128 bits of data sent are required to be latched for display). The pulse on the ENB pin must occur while DCLK is high. DCLK, Din Data Clock and Data Input (Pins 38, 39) Address input and data input controls. See Data Input Protocol sections for relevant option. OSC1, OSC2 Oscillator Pins (Pins 51, 50) To use the on–board oscillator, an external resistor should be connected between OSC1 and OSC2 of the master device. Optionally, the OSC1 pin of the master device may be driven by an externally generated clock signal. The oscillator signal for any slave(s) in the system is provided by the master device by connecting the master’s OSC2 pin to the slaves’(s) OSC2 pin(s). The slaves’(s) OSC1 pin(s) should be connected to ground. A resistor of 680 k Ω connected between the master’s OSC1 and OSC2 pins gives an oscillator frequency of about 30 kHz, giving approximately 30 Hz as seen at the LCD driver outputs. A resistor of 200 k Ω gives about 100 kHz, which results in 100 Hz at the driver outputs. LCD manufacturers recommend an LCD drive frequency of between 30 Hz and 100 Hz. See Figure 6. 1 k 10 k 100 k 1 M 10 M 10 M 1 M 100 k 10 k OSCILLATOR FREQUENCY Figure 6. Oscillator Frequency vs Load Resistance (Approximate) FS Frame Sync (Pin 37) The frame sync pin (FS) is configured as an output on the master device and as an input on the slave device(s). The master device outputs a pulse on the FS pin once at the begin- ning of each BP1 (backplane 1) active period to keep all MC145003/MC145004s synchronized. FP1–FP32 Frontplane Drivers (Pins 36–27, 25–22, 19–15, 13–1) Frontplane driver outputs. BP1–BP4 Backplane Drivers (Pins 48–45) Backplane driver outputs. VLCD LCD Driver Supply (Pin 20) Power supply input for LCD drive outputs. May be used to supply a temperature–compensated voltage to the LCD drive section, which can be separate from the logic voltage supply, VDD. |
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Mô tả tương tự - MC145003 |
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