AD1970

Rev. 0 | Page 8 of 20

Pin No.

Pin Name

Input/Output

Description

18

VIN_IAMPR

IN

Negative input of internal op amp for right channel input amplifier.

19

CAPLP

I/O

ADC Filter Capacitor Connection (positive left-channel input to modulator). A 1 nF

capacitor should be placed between this pin and analog ground.

20

CAPLN

I/O

ADC Filter Capacitor Connection (negative left-channel input to modulator). A 1 nF

capacitor should be placed between this pin and analog ground.

21

CAPRP

I/O

ADC Filter Capacitor Connection (positive right-channel input to modulator). A 1 nF

capacitor should be placed between this pin and analog ground.

22

CAPRN

I/O

ADC Filter Capacitor Connection (negative right-channel input to modulator). A 1 nF

capacitor should be placed between this pin and analog ground.

23

PVDD

PLL Power. 3.3 V nominal. Bypass capacitors should be placed close to this pin and

connected directly to the PLL ground.

24

PLL_LF

PLL Loop Filter Connection.

25

PGND

PLL Ground. Connect to DGND.

26

VID_IN

IN

Composite Video Input. Composite video signal input to the sync separator. The sync

output is connected to a PLL that generates the clocks for the AD1970. This pin has an

input impedance of 2 kΩ.

27

NC

No Connect.

28

PLL_MODE0

IN

PLL Mode Select Pin 0. The setting of these pins indicates the source and frequency of the

input clock to generate the internal MCLK for the AD1970.

29

PLL_MODE1

IN

PLL Mode Select Pin 1. The setting of these pins indicates the source and frequency of the

input clock to generate the internal MCLK for the AD1970.

30

MCLK

IN

Master Clock Input. This input is used to generate the internal master clock if it is not

derived from the composite video signal on VID_IN. The master clock frequency must be

either fs or 256 × fs, where fs is the input sampling frequency. The PLL_CTRLx pins should

be set to accept the appropriate MCLK input frequency.

31

VID_PRES

OUT

Video Present Flag. A high logic level on this pin indicates that a valid composite video

signal is present on the VID_IN pin. Open-drain output.

32

XOUT

OUT

Crystal Oscillator Output. This pin is the output of the on-board oscillator and should be

connected to one side of a crystal.

33

XIN

IN

Crystal Oscillator Input. This pin is the input to the on-board oscillator and should be

connected to one side of a crystal.

34

GPIO0

IN/OUT

General Purpose I/O 0. This pin can be set to be either a static input or output, with levels

35

GPIO1

IN/OUT

General Purpose I/O 1. This pin can be set to be either a static input or output, with levels

36

DGND

Digital Ground.

37

DVDD

Digital Power.

38

GPIO2

IN/OUT

General Purpose I/O 2. This pin can be set to be either a static input or output, with levels

39

GPIO3

IN/OUT

General Purpose I/O 3. This pin can be set to be either a static input or output, with levels

40

SDATA

IN/OUT

Serial Data Input/Output (Before BTSC Encoding). Digital input to the BTSC encoder or

output of the ADC. The serial format is selected by writing to Bits 3:2 of Control Register 1.

41

BCLK

IN/OUT

Bit Clock Input/Output. Serial bit clock for clocking in the serial data. The interpretation of

BCLK changes according to the serial mode, which is set by writing to the control

registers.

42

LRCLK

IN/OUT

Left/Right Clock Input/Output. Left/right clock for framing the serial input data. The

interpretation of the LRCLK changes according to the serial mode, set by writing to the

control registers.

43

DIG_IN_EN

IN

Digital Input Enable (active high).

44

SDA

IN/OUT

45

SCL

IN

46

ADR1

IN

47

ADR0

IN

48

DGND

Digital Ground.