MC100EP91DWG datasheet(2/10 Pages) ONSEMI

tên linh kiện	MC100EP91DWG

Giải thích chi tiết về linh kiện	2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator

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MC100EP91

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2

D1

D2

Q0

Q1

VEE

D0

Q0

D2

D0

VCC

Figure 1. Logic Diagram

Q2

GND

VBB

Positive Level

Input

NECL Output

R1

R2

Table 1. PIN DESCRIPTION

Name

I/O

Default

State

Description

SOIC

QFN

1, 20

3, 4, 12

VCC

−

Positive Supply Voltage. All VCC Pins must be Externally

Connected to Power Supply to Guarantee Proper Opera-

tion.

10

15, 16

VEE

−

Negative Supply Voltage. All VEE Pins must be Externally

Connected to Power Supply to Guarantee Proper Opera-

tion.

14, 17

19, 20, 23,

24

GND

−

Ground.

4, 7

7, 11

VBB

−

ECL Reference Voltage Output

2, 5, 8

5, 8, 13

D[0:2]

LVPECL, LVDS, LVTTL,

LVCMOS, CML, HSTL Input

Low

Noninverted Differential Inputs [0:2]. Internal 75 kW to VEE.

3, 6, 9

6, 9, 14

D[0:2]

LVPECL, LVDS,

LVTTL,LVCMOS, CML,

HSTL Input

High

Inverted Differential Inputs [0:2]. Internal 75 kW to VEE and

75 kW to VCC. When Inputs are Left Open They Default to

(VCC − VEE) / 2.

19,16,13

2, 18, 22

Q[0:2]

NECL Output

−

Noninverted Differential Outputs [0:2]. Typically Terminated

with 50 W to VTT = VCC − 2 V

18,15,12

1, 21, 17

Q[0:2]

NECL Output

−

Inverted Differential Outputs [0:2]. Typically Terminated with

50 W to VTT = VCC − 2 V

11

10

NC

−

No Connect. The NC Pin is NOT Electrically Connected to

the Die and may Safely be Connected to Any Voltage from

VEE to VCC.

N/A

−

EP

−

Exposed Pad. (Note 1)

1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat−sinking conduit.

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ON Semiconductor	MC100EP91DWG	181Kb / 10P	Any Level Positive Input to NECL Output Translator August, 2016 ??Rev. 6

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Texas Instruments	SN74AUP1T02	164Kb / 11P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT,SINGLE 2-INPUT POSITIVE-NOR GATE

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