ADM1067ACP-REEL datasheet(5/32 Pages) AD

tên linh kiện	ADM1067ACP-REEL

Giải thích chi tiết về linh kiện	Super Sequencer with Open-Loop Margining DACs

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ADM1067

Rev. B | Page 5 of 32

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Gain Error

1

%

Maximum Load Current (Source)

100

μA

Maximum Load Current (Sink)

100

μA

Maximum Load Capacitance

50

pF

Settling Time into 50 pF Load

2

μs

Load Regulation

2.5

mV

Per mA

PSRR

60

dB

DC

40

dB

100 mV step in 20 ns with 50 pF load

REFERENCE OUTPUT

Reference Output Voltage

2.043

2.048

2.053

V

No load

Load Regulation

−0.25

mV

Sourcing current, IDACnMAX =

−100 μA

0.25

mV

Sinking current, IDACnMAX = 100 μA

Minimum Load Capacitance

1

μF

Capacitor required for decoupling, stability

PSRR

60

dB

DC

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDO1 to PDO6)

Output Impedance

500

kΩ

VOH

11

12.5

14

V

IOH = 0

10.5

12

13.5

V

IOH = 1 μA

IOUTAVG

20

μA

2 V < VOH < 7 V

Standard (Digital Output) Mode

(PDO1 to PDO10)

VOH

2.4

V

VPU (pull-up to VDDCAP or VPn) = 2.7 V, IOH = 0.5 mA

4.5

V

VPU to VPn = 6.0 V, IOH = 0 mA

VPU −

0.3

V

VPU ≤ 2.7 V, IOH = 0.5 mA

VOL

0

0.50

V

IOL = 20 mA

IOL2

20

mA

Maximum sink current per PDO pin

ISINK2

60

mA

Maximum total sink for all PDOs

RPULL-UP

16

20

29

kΩ

Internal pull-up

ISOURCE (VPn)2

2

mA

Current load on any VPn pull-ups, that is, total source current

available through any number of PDO pull-up switches

configured onto any one

Three-State Output Leakage Current

10

μA

VPDO = 14.4 V

Oscillator Frequency

90

100

110

kHz

All on-chip time delays derived from this clock

DIGITAL INPUTS (VXn, A0, A1, MUP, MDN)

Input High Voltage, VIH

2.0

V

Maximum VIN = 5.5 V

Input Low Voltage, VIL

0.8

V

Maximum VIN = 5.5 V

Input High Current, IIH

−1

μA

VIN = 5.5 V

Input Low Current, IIL

1

μA

VIN = 0

Input Capacitance

5

pF

Programmable Pull-Down Current,

IPULL-DOWN

20

μA

VDDCAP = 4.75, TA = 25°C, if known logic state is required

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH

2.0

V

Input Low Voltage, VIL

0.8

V

Output Low Voltage, VOL2

0.4

V

IOUT = −3.0 mA

SERIAL BUS TIMING

Clock Frequency, fSCLK

400

kHz

Bus Free Time, tBUF

4.7

μs

Start Setup Time, tSU;STA

4.7

μs

Start Hold Time, tHD;STA

4

μs

SCL Low Time, tLOW

4.7

μs

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