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AM29DL323CT90 bảng dữ liệu(PDF) 10 Page - Advanced Micro Devices |
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10 / 52 page Am29DL322C/Am29DL323C 10 ADV ANCE I N FO RMAT I O N this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (I CC4). If RESET# is held at V IL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RE- SET# pin returns to V IH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. Am29DL322C/Am29DL323C Device Bank Divisions Device Part Number Bank 1 Bank 2 Megabits Sector Sizes Megabits Sector Sizes Am29DL322C 4 Mbit Eight 8 Kbyte/4 Kword, seven 64 Kbyte/32 Kword 28 Mbit Fifty-six 64 Kbyte/32 Kword Am29DL323C 8 Mbit Eight 8 Kbyte/4 Kword, fifteen 64 Kbyte/32 Kword 24 Mbit Forty-eight 64 Kbyte/32 Kword |
Số phần tương tự - AM29DL323CT90 |
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Mô tả tương tự - AM29DL323CT90 |
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