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ADV7341EBZ bảng dữ liệu(PDF) 7 Page - Analog Devices |
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7 / 88 page ADV7340/ADV7341 Rev. 0 | Page 7 of 88 DIGITAL TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 7. Parameter Conditions1 Min Typ Max Unit VIDEO DATA AND VIDEO CONTROL PORT2, 3 Data Setup Time, t114 SD 2.1 ns ED/HD-SDR 2.3 ns ED/HD-DDR 2.3 ns ED (at 54 MHz) 1.7 ns Data Hold Time, t124 SD 1.0 ns ED/HD-SDR 1.1 ns ED/HD-DDR 1.1 ns ED (at 54 MHz) 1.0 ns Control Setup Time, t114 SD 2.1 ns ED/HD-SDR or ED/HD-DDR 2.3 ns ED (at 54 MHz) 1.7 ns Control Hold Time, t124 SD 1.0 ns ED/HD-SDR or ED/HD-DDR 1.1 ns ED (at 54 MHz) 1.0 ns Digital Output Access Time, t134 SD 12 ns ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 10 ns Digital Output Hold Time, t144 SD 4.0 ns ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 3.5 ns PIPELINE DELAY5 SD1 CVBS/YC Outputs (2×) SD oversampling disabled 68 clock cycles CVBS/YC Outputs (16×) SD oversampling enabled 67 clock cycles Component Outputs (2×) SD oversampling disabled 78 clock cycles Component Outputs (16×) SD oversampling enabled 84 clock cycles ED1 Component Outputs (1×) ED oversampling disabled 41 clock cycles Component Outputs (8×) ED oversampling enabled 46 clock cycles HD1 Component Outputs (1×) HD oversampling disabled 40 clock cycles Component Outputs (4×) HD oversampling enabled 44 clock cycles 1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate. 2 Video data: C[9:0], Y[9:0], and S[9:0]. 3 Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC. 4 Guaranteed by characterization. 5 Guaranteed by design. |
Số phần tương tự - ADV7341EBZ |
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Mô tả tương tự - ADV7341EBZ |
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