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AM29BDS64HE8VMI bảng dữ liệu(PDF) 11 Page - SPANSION |
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11 / 89 page May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 9 D A TA SH EE T INPUT/OUTPUT DESCRIPTIONS Amax–A0 = Address inputs Amax = A22 (128 Mb) or A21 (64 Mb) DQ15–DQ0 = Data input/output CE# = Chip Enable input. Asynchronous relative to CLK for the Burst mode. OE# = Output Enable input. Asynchronous relative to CLK for the Burst mode. WE# = Write Enable input. VCC = Device Power Supply (1.65 – 1.95 V). VIO = Input & Output Buffer Power Supply (1.65 – 1.95 V). VSS =Ground NC = No Connect; not connected internally RDY = Ready output; In Synchronous Mode, indicates the status of the Burst read. Low = data invalid. High = data valid. In Asynchronous Mode, indicates the status of the internal program and erase function. Low = program/erase in progress. High Impedance = program/erase completed. CLK = CLK is not required in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. AVD# = Address Valid input. Indicates to device that the valid address is present on the address inputs (Amax–A0). Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs RESET# = Hardware reset input. Low = device resets and returns to reading array data WP# = Hardware write protect input. At VIL, disables program and erase functions in the four highest and four lowest sectors. At VIH, does not protect any sectors. ACC = At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, locks all sectors. Should be at VIH for all other conditions. LOGIC SYMBOL 23 or 22 16 DQ15–DQ0 Amax–A0 CE# OE# WE# RESET# CLK RDY AVD# WP# ACC |
Số phần tương tự - AM29BDS64HE8VMI |
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Mô tả tương tự - AM29BDS64HE8VMI |
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