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ADAU1702JSTZ bảng dữ liệu(PDF) 5 Page - Analog Devices |
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ADAU1702JSTZ bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 52 page ADAU1702 Rev. 0 | Page 5 of 52 REGULATOR Table 6. Regulator1 Parameter Min Typ Max Unit DVDD Voltage 1.7 1.8 1.84 V 1 Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit. DIGITAL TIMING SPECIFICATIONS Table 7. Digital Timing1 Limit Parameter TMIN TMAX Unit Description MASTER CLOCK tMP 36 244 ns MCLK period, 512 fS mode. tMP 48 366 ns MCLK period, 384 fS mode. tMP 73 488 ns MCLK period, 256 fS mode. tMP 291 1953 ns MCLK period, 64 fS mode. SERIAL PORT tBIL 40 ns INPUT_BCLK low pulse width. tBIH 40 ns INPUT_BCLK high pulse width. tLIS 10 ns INPUT_LRCLK setup. Time to INPUT_BCLK rising. tLIH 10 ns INPUT_LRCLK hold. Time from INPUT_BCLK rising. tSIS 10 ns SDATA_INx setup. Time to BCLK_IN rising. tSIH 10 ns SDATA_INx hold. Time from BCLK_IN rising. tLOS 10 ns OUTPUT_LRCLK setup in slave mode. tLOH 10 ns OUTPUT_LRCLK hold in slave mode. tTS 5 ns OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew. tSODS 40 ns SDATA_OUTx delay. Time from OUTPUT_BCLK falling in slave mode. tSODM 40 ns SDATA_OUTx delay. Time from OUTPUT_BCLK falling in master mode. SPI PORT fCCLK 6.25 MHz CCLK frequency. tCCPL 80 ns CCLK pulse width low. tCCPH 80 ns CCLK pulse width high. tCLS 0 ns CLATCH setup. Time to CCLK rising. tCLH 100 ns CLATCH hold. Time from CCLK rising. tCLPH 80 ns CLATCH pulse width high. tCDS 0 ns CDATA setup. Time to CCLK rising. tCDH 80 ns CDATA hold. Time from CCLK rising. tCOD 101 ns COUT delay. Time from CCLK falling. I2C PORT fSCL 400 kHz SCL frequency. tSCLH 0.6 μs SCL high. tSCLL 1.3 μs SCL low. tSCS 0.6 μs Setup time, relevant for repeated start condition. tSCH 0.6 μs Hold time. After this period, the first clock is generated. tDS 100 ns Data setup time. tSCR 300 ns SCL rise time. tSCF 300 ns SCL fall time. tSDR 300 ns SDA rise time. tSDF 300 ns SDA fall time. tBFT 0.6 Bus-free time. Time between stop and start. |
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