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MCF5212 bảng dữ liệu(PDF) 6 Page - Freescale Semiconductor, Inc |
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MCF5212 bảng dữ liệu(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 56 page MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2 Preliminary MCF5213 Family Configurations Freescale Semiconductor 6 — Global network time, synchronized by a specific message — Maskable interrupts • Three universal asynchronous/synchronous receiver transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic with maskable interrupts — DMA support — Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity — Up to 2 stop bits in 1/16 increments — Error-detection capabilities — Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs — Transmit and receive FIFO buffers •I2C module — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I2C bus — Master and slave modes support multiple masters — Automatic interrupt generation with programmable level • Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to four chip selects available — Master mode operation only — Programmable bit rates up to half the CPU clock frequency — Up to 16 pre-programmed transfers • Fast analog-to-digital converter (ADC) — Eight analog input channels — 12-bit resolution — Minimum 1.125 µs conversion time — Simultaneous sampling of two channels for motor control applications — Single-scan or continuous operation — Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit — Unused analog channels can be used as digital I/O • Four 32-bit DMA timers — 12.5-ns resolution at 80 MHz — Programmable sources for clock input, including an external clock option — Programmable prescaler |
Số phần tương tự - MCF5212 |
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Mô tả tương tự - MCF5212 |
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