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MCF52223 bảng dữ liệu(PDF) 11 Page - Freescale Semiconductor, Inc

tên linh kiện MCF52223
Giải thích chi tiết về linh kiện  Microcontroller Data Sheet
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MCF52223 bảng dữ liệu(HTML) 11 Page - Freescale Semiconductor, Inc

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MCF52223 Family Configurations
MCF52223 ColdFire® Microcontroller Data Sheet, Rev. 1
Preliminary
Freescale Semiconductor
11
1.2.5
Power Management
The MCF52223 incorporates several low power modes of operation which are entered under program
control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors
the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)
monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the
LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip
falls below the standby battery voltage.
1.2.6
USB On-the-Go Controller
The USB controller is programmable to support host, device or On-the-Go operations. The dual-role
feature allows device-to-device connectivity, without the need for a host PC (e.g. digital camera to photo
printer).
For more details, the following specifications can be found from the ULPI web page at http://www.ulpi.org
1.2.7
UARTs
The MCF52223 has three full-duplex UARTs that function independently. The three UARTs can be
clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages,
the third UART is multiplexed with other digital I/O functions.
1.2.8
I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange
and minimizes the interconnection between devices. This bus is suitable for applications requiring
occasional communications over a short distance between many devices.
1.2.9
QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with
queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU
intervention between transfers.
1.2.10 Fast ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold
(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible
buffers for further processing.
The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or
perform a programmed scan sequence repeatedly until manually stopped.
The ADC can be configured for either sequential or simultaneous conversion. When configured for
sequential conversions, up to eight channels can be sampled and stored in any order specified by the
channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.


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