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ADM1177 bảng dữ liệu(PDF) 4 Page - Analog Devices |
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ADM1177 bảng dữ liệu(HTML) 4 Page - Analog Devices |
4 / 16 page ADM1177 Preliminary Technical Data Rev. PrD | Page 4 of 16 Parameter Min Typ Max Units Conditions MONITORING ACCURACY1 Current Sense Absolute Accuracy TBD TBD % VSENSE = 75 mV −2.3 +2.2 % VSENSE = 75 mV, @ 0°C to +70°C TBD TBD % VSENSE = 50mV −2.5 +2.5 % VSENSE = 50 mV, @ 0°C to +70°C TBD TBD % VSENSE = 25mV −2.8 +2.8 % VSENSE = 25mV, @ 0°C to +70°C −3.5 +3.5 % VSENSE = 12.5 mV, @ 25°C Current Sense Accuracy, TC ±0.01 %/°C VSENSE for ADC full-scale 105 mV Voltage Sense Accuracy −1.5 0 +1.5 % VVCC = 3.0 V to 5.5V(VRANGE = 1) −1.5 0 +1.5 % VVCC = 10.8 V to 13.2V(VRANGE = 0) VCC for ADC full-scale, low range 6.656 V VRANGE = 1 VCC for ADC full-scale, high range 26.6282 V VRANGE = 0 I2C Timing3 Low level input voltage, VIL 0.99 V High level input voltage, VIH 2.31 V Low level output voltage on SDA, VOL 0.4 V IOL = 3mA Output fall time on SDA from VIHMIN to VILMAX 20+0.1CB 250 ns CB = bus capacitance from SDA to GND Maximum width of spikes suppressed by input filtering on SDA and SCL pins 50 250 ns Input current, II, on SDA/SCL when not driving out a logic low −10 +10 µA Input capacitance on SDA/SCL 5 pF SCL clock frequency, fSCL 400 kHz LOW period of the SCL clock 600 ns HIGH period of the SCL clock 1300 ns Setup time for a repeated START condition, tSU;STA 600 ns SDA output data hold time, tHD;DAT 100 ns Set-up time for a stop condition, tSU;STO 600 ns Bus free time between a STOP and a START condition, tBUF 1300 ns Capacitive load for each bus line 400 pF 1 Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error and ADC error. 2The maximum operating voltage is limited to VVCC =14 V which corresponds to an ADC code of 871. 3The following conditions apply to all timing specifications: VBUS =3.3V, TA =25°C. All timings refer to VIHMIN and VILMAX. |
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