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LM5069 bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
tên linh kiện LM5069
Giải thích chi tiết về linh kiện  Positive High Voltage Hot Swap / Inrush Current Controller with Power Limiting
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nhà sản xuất  NSC [National Semiconductor (TI)]
Trang chủ  http://www.national.com
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LM5069 bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI)

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Electrical Characteristics Limits in standard type are for T
J = 25˚C only; limits in boldface type apply over the
junction temperature (T
J) range of -40˚C to +125˚C. Minimum and Maximum limits are guaranteed through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at T
J = 25˚C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 48V. (Continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Current Limit
V
CL
Threshold voltage
VIN-SENSE voltage
48.5
55
61.5
mV
t
CL
Response time
VIN-SENSE stepped from 0 mV to
80 mV
45
µs
I
SENSE
SENSE input current
Enabled, SENSE = OUT
23
µA
Disabled, OUT = 0V
60
Circuit Breaker
V
CB
Threshold voltage
VIN - SENSE
80
105
130
mV
t
CB
Response time
VIN - SENSE stepped from 0 mV
to 150 mV, time to GATE low, no
load
0.44
1.2
µs
Timer (TIMER pin)
V
TMRH
Upper threshold
3.76
4
4.16
V
V
TMRL
Lower threshold
Restart cycles (LM5069-2)
1.187
1.25
1.313
V
End of 8th cycle (LM5069-2)
0.3
V
Re-enable Threshold (LM5069-1)
0.3
V
I
TIMER
Insertion time current
3
5.5
8
µA
Sink current, end of insertion time
TIMER pin = 2V
1.0
1.5
2.0
mA
Fault detection current
51
85
120
µA
Fault sink current
1.25
2.5
3.75
µA
DC
FAULT
Fault Restart Duty Cycle
LM5069-2 only
0.5
%
t
FAULT
Fault to GATE low delay
TIMER pin reaches 4.0V
12
µs
Power Good (PGD pin)
PGD
TH
Threshold measured at SENSE-OUT
Decreasing
0.67
1.25
1.85
V
Increasing, relative to decreasing
threshold
0.95
1.25
1.55
PGD
VOL
Output low voltage
I
SINK =2mA
60
150
mV
PGD
IOH
Off leakage current
V
PGD = 80V
5
µA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 k
Ω resistor into each pin.
Note 3: OUT bias current (disabled) due to leakage current through an internal 1.0 M
Ω resistance from SENSE to VOUT.
Note 4: For detailed information on soldering plastic MSOP packages refer to the Packaging Databook available from National Semiconductor Corporation.
Note 5: The GATE pin voltage is typically 12V above VIN when the LM5069 is enabled. Therefore the Absolute Maximum Ratings for VIN (100V) applies only when
the LM5069 is disabled, or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is also 100V.
www.national.com
4


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