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ADM1062ACP bảng dữ liệu(PDF) 7 Page - Analog Devices

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Giải thích chi tiết về linh kiện  Multisupply Supervisor/Sequencer with Margining Control and Temperature Monitoring
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Preliminary Technical Data
ADM1062
Rev. PrJ | Page 7 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
4.5
V
VPU to Vpn = 6.0V, IOH = 0mA
VPU−0.3
V
VPU< = 2.7V, IOH = 1mA
VOL
0.1
V
IOL = 4mA
0.25
V
IOL = 10mA
0.5
V
IOL = 20mA
IOL
20
mA
Max sink current per PDO pin
ISINK
60
mA
Max total sink for all PDOs
RPULLUP
20
kΩ
Internal pullup
ISOURCE(VPn)
2
mA
Current Load on any VPn pull- ups (ie) total source current
available through any number of PDO pull-up switches
configured on to any one
Tristate Output Leakage
Current
10
µA
VPDO= 14.4V
DIGITAL INPUTS (VXn,A0,A1)
Input High Voltage, VIH
2.0
V
Max. VIN=5.5V
Input Low Voltage, VIL
0.8
V
Max. VIN=5.5V
Input High Current, IIH
−1
µA
VIN= 5.5V
Input Low Current, IIL
1
µA
VIN= 0
Input Capacitance
TBD
pF
Programmable Pulldown
Current, IPULLDOWN
10
µA
If known logic state required
SERIAL BUS DIGITAL INPUTS
(SDA,SCL)
Input High Voltage, VIH
2.0
V
Input Low Voltage, VIL
0.8
V
Output Low Voltage, VOL
0.4
V
IOUT = -3.0mA
SERIAL BUS TIMING
Clock Frequency, fSCLK
400
KHz
Bus Free Time, tBUF
4.7
µs
Start Setup Time, tSU;STA
4.7
µs
Start Hold Time, tHD;STA
4
µs
SCL Low Time, tLOW
4.7
µs
SCL High Time, tHIGH
4
µs
SCL, SDA Rise Time, tr
1000
µs
SCL, SDA Fall Time, tf
300
µs
Data Setup Time, tSU;DAT
250
ns
Data Hold Time, tHD;DAT
300
ns
1 These are target specifications and subject to change.
2 At least one of the VH, VP1-4 pins must be
≥ 3.0V to maintain device supply on VDDCAP.
3 Guaranteed by Characterization.
4 Guaranteed by Design.


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