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ADM1062 bảng dữ liệu(PDF) 8 Page - Analog Devices

tên linh kiện ADM1062
Giải thích chi tiết về linh kiện  Multisupply Supervisor/Sequencer with Margining Control and Temperature Monitoring
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ADM1062
Preliminary Technical Data
Rev. PrJ | Page 8 of 32
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
Figure 3. LFCSP Pin Configuration
Figure 4. TQFP Pin Configuration
Table 2. Pin Functional Descriptions
Pin Number
LFCSP
TQFP
Mnemonic
Description
1
NC
No connection.
1–5
2-6
VX1–5
High impedance inputs to supply fault detectors. Fault thresholds can be set at between
0.573V and 1.375V. Alternatively these pins can be used as general purpose digital inputs.
6–9
7-10
VP1–4
Low voltage inputs to supply fault detectors. Three input ranges can be set by altering the
input attenuation on a potential divider connected to these pins, the output of which connects
to a supply fault detector; these allow thresholds between 2.5V-6V, 1.25V-3V and 0.573V-
1.375V.
10
11
VH
High voltage input to supply fault detectors. Three input ranges can be set by altering the
input attenuation on a potential divider connected to this pin, the output of which connects to
a supply fault detector; these allow thresholds between 6V-14.4V,2.5V-6V and 1.25V-3V.
12-13
NC
No connection.
11
14
AGND
Ground return for input attenuators.
12
15
REFGND
Ground return for on-chip reference circuits.
13
16
REFIN
Reference input for ADC, nominally 2.048V.
14
17
REFOUT
2.048V reference output.
15–20
18-23
DAC1–6
Voltage output DACs. Default to high impedance at power-up.
24-25
NC
No connection.
21–30
26-35
PDO10–1
Programmable output drivers.
36-37
NC
No connection.
31
38
PDOGND
Ground return for output drivers
32
39
VCCP
Central charge pump voltage of 5.25V. A reservoir capacitor must be connected between this
pin and GND.
33
40
A0
Logic input which sets the 7th bit of the SMBus interface address.
34
41
A1
Logic input which sets the 6th bit of the SMBus interface address.
35
42
SCL
SMBus clock pin. Open drain output requiring external resistive pull-up.
36
43
SDA
SMBus data i/o pin. Open drain output requiring external resistive pull-up.
37
44
DN
External Thermal Diode Cathode Connection
38
45
DP
External Thermal Diode Anode Connection
39
46
VDDCAP
Device supply voltage. Linearly regulated from the highest of the VP1-4,VH pins and clamped
to a maximum of 4.75V
40
47
GND
Supply ground.
48
NC
No connection.


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