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ADAU1701JSTZ bảng dữ liệu(PDF) 5 Page - Analog Devices

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ADAU1701JSTZ bảng dữ liệu(HTML) 5 Page - Analog Devices

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Preliminary Technical Data
ADAU1701
Rev. PrF | Page 5 of 43
Parameter
Min
Typical
Max
Units
Test Conditions/Comments
Gain Error
TBD
%
DC Bias
1.5
V
Power Supply Rejection
TBD
dB
1kHz, 300mVP-P Signal at AVDD
DIGITAL I/O
Table 3. Digital I/O
Parameter
Min
Typ
Max
Unit
Input Voltage, HI (VIH)
2.0
IOVDD
V
Input Voltage, LO (VIL)
0.8
V
Input Leakage, HI (IIH)
10
μA
Input Leakage, LO (IIL)
10
μA
High Level Output Voltage (VOH), IOH = 1 mA
2.0
V
Low Level Output Voltage (VOL), IOL = 1 mA
0.8
V
Input Capacitance
5
pF
GPIO Output Drive
5
mA
POWER
Table 4.
Parameter
Comments
Min
Typ
Max1
Unit
Supply Voltage
Analog Voltage
3.3
V
Digital Voltage
1.8
V
PLL Voltage
3.3
V
IOVDD Voltage
3.3
V
Supply Current
Analog Current (AVDD & PVDD)
65
85
mA
Digital Current (DVDD)
40
60
mA
PLL Current
TBD
mA
Analog Current, Reset
TBD
mA
Digital Current, Reset
TBD
mA
PLL Current, Reset
TBD
mA
Dissipation
Operation (AVDD, DVDD, PVDD)2
286.5
mW
Reset, all supplies
TBD
mW
1 Maximum specifications are measured across
−xx°C to xx°C (case) and across VDD = xxx V to xxx V.
2 Power dissipation does not include IOVDD power because the current draw from this supply is dependant on loads on the digital output pins.
TEMPERATURE RANGE
Table 5.
Parameter
Min
Typ
Max
Unit
Functionality Guaranteed
0°C
70°C
°C Ambient
DIGITAL TIMING
Table 6 Digital Timing1
Parameter
Comments
Min
Max
Unit
MASTER CLOCK
tMP
MCLK Period
512 fS mode
36
244
ns
tMP
MCLK Period
384 fS mode
48
366
ns
tMP
MCLK Period
256 fS mode
73
488
ns
tMP
MCLK Period
64 fS mode
291
1953
ns
SERIAL PORT
tBIL
INPUT_BCLK LO Pulse Width
40
ns
tBIH
INPUT_BCLK HI Pulse Width
40
ns
tLIS
INPUT_LRCLK Setup
To INPUT_BCLK rising
10
ns
tLIH
INPUT_LRCLK Hold
From INPUT_BCLK rising
10
ns


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