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MC145422DW bảng dữ liệu(PDF) 9 Page - Motorola, Inc |
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MC145422DW bảng dữ liệu(HTML) 9 Page - Motorola, Inc |
9 / 20 page MC145422 •MC145426 MOTOROLA 9 MC145422 MASTER UDLT PIN DESCRIPTIONS VDD Positive Supply Normally 5 V. VSS Negative Supply This pin is the most negative supply pin, normally 0 V. Vref Reference Output This pin is the output of the internal reference supply and should be bypassed to VDD and VSS by 0.1 µF capacitors. No external dc load should be placed on this pin. LI Line Input This input to the demodulator circuit has an internal 100 k Ω resistor tied to the internal reference node so that an external capacitor and/or line transformer may be used to couple the input signal to the part with no dc offset. LB Loopback Control A low on this pin disconnects the LI pin from internal cir- cuitry, drives LO1, LO2 to Vref and internally ties the modu- lator output to the demodulator input which loops the part on itself for testing in the system. The state of this pin is inter- nally latched if the SE pin is brought and held low. Loopback is active only when PD Is high. VD Valid Data Output A high on this pin indicates that a valid line transmission has been demodulated. A valid transmission is determined by proper sync and the absence of detected bit errors. VD changes state on the leading edge of MSI when PD is high. When PD is low, VD changes state at the end of demodula- tion of a line transmission. VD is a standard B–series CMOS output and is high impedance when SE is held low. SI1, SI2 Signaling Bit Inputs Data on these pins is loaded on the rising edge of MSI for transmission to the slave. The state of these pins is internally latched if SE is held low. SO1, SO2 Signaling Bit Outputs These outputs are received signaling bits from the slave UDLT and change state on the rising edge of MSI if PD is high, or at the completion of demodulation if PD is low. These outputs have standard B–series CMOS drive capability and are high impedance if the SE pin is held low. SE Signal Enable Input If held high, the PD, LB, SI1, SI2, and SIE inputs and the SO1, SO2, and VD outputs function normally. If held low, the state of these inputs is latched and held internally while the outputs are high impedance. This allows these pins to be bussed with those of other UDLTs to a common controller. PD Power–Down Input If held low, the UDLT ceases modulation. In power–down, the only active circuit is that which is necessary to demodu- late an incoming burst and output the signal and valid data bits. Internal data transfers to the transmit and receive regis- ters cease. When brought high, the UDLT powers up, and waits three positive MSI edges or until the end of an incom- ing transmission from the slave UDLT and begins transmit- ting every MSI period to the slave UDLT on the next rising edge of the MSI. MSI Master Sync Input This pin is the system sync and initiates the modulation on the twisted pair. MSI should be approximately leading–edge aligned with TDC/RDC. SIE Signal Insert Enable This pin, when held high, inserts signal bit 2 received from the slave into the LSB of the outgoing PCM word at Tx and will ignore the SI2 pin and use in place the LSB of the incom- ing PCM word at Rx for transmission to the slave. The PCM word to the slave will have LSB forced low in this mode. In this manner, signal bit 2 to/from the slave UDLT is inserted in to the PCM words the master sends and receives from the backplane for routing through the PABX for simultaneous voice/data communication. The state of this pin is internally latched if the SE pin is brought and held low. TE1 Transmit Data Enable 1 Input This pin controls the outputting of data on the Tx pin. While TE1 is high, the Tx data is presented on the eight rising edges of TDC/RDC. TE1 is also a high–impedance control of the Tx pin. If MSI occurs during this period, new data will be transferred to the Tx output register in the ninth high period of TDC/RDC after TE1 rises; otherwise, it will transfer on the rising edge of MSI. TE1 and TDC/RDC should be approxi- mately leading–edge aligned. Tx Transmit Data Output This three–state output presents new voice data during the high periods of TDC/RDC when TE1 is high (see TE1). CCI Convert Clock Input A 2.048 MHz clock signal should be applied to this pin. The signal is used for internal sequencing and control. This signal should be coherent with MSI for optimum performance but may be asynchronous if slightly worse error rate perform- ance can be tolerated. TDC/RDC Transmit/Receive Data Clock This pin is the transmit and receive data clock and can be 64 kHz to 2.56 MHz. Data is output at the Tx pin while TE1 is high on the eight rising edges of TDC/RDC after the rising edge of TE1. Data on the Rx pin is loaded into the receive register of the UDLT on the eight falling edges of TDC/RDC after a positive transition on RE1. This clock should be ap- proximately leading–edge aligned with MSI. |
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