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SN74V263-10PZA bảng dữ liệu(PDF) 3 Page - Texas Instruments

tên linh kiện SN74V263-10PZA
Giải thích chi tiết về linh kiện  819218, 1638418, 3276818, 65536 횞 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
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SN74V263-10PZA bảng dữ liệu(HTML) 3 Page - Texas Instruments

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SN74V263, SN74V273, SN74V283, SN74V293
8192
× 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
B
C
D
E
F
G
H
J
K
123
4567
8
9
10
VCC
VCC
VCC
NC
VCC
VCC
VCC
VCC
VCC
VCC
NC
WCLK
PRS
LD
GND
BE
PFM
RCLK
RT
SEN
WEN
MRS
FF/IR
FSEL0
FSEL1
PAE
RM
REN
OE
DNC
DNC
VCC
FWFT/
SI
OW
HF
IP
EF/OR
Q17
GND
GND
GND
GND
GND
IW
D17
PAF
NC
Q16
D16
D15
GND
GND
Q15
Q14
D14
D13
GND
VCC
Q13
Q12
NC
D12
D11
VCC
Q2
GND
GND
GND
Q11
D10
D9
D5
D1
Q0
GND
VCC
Q9
Q10
D8
D7
GND
GND
D3
Q1
Q3
Q5
Q7
Q8
D6
D4
D2
D0
GND
GND
Q4
Q6
DNC = Do not connect
GGM PACKAGE
(TOP VIEW)
A
NC
NC
NC
NC
description (continued)
The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence.
There are no restrictions on the frequency of one clock input with respect to the other.
There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and
standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three
transitions of the RCLK signal. REN need not be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a low on REN for access. The state of the FWFT/SI input during master
reset determines the timing mode in use.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a
specific read operation is performed. A read operation, which consists of activating REN and enabling a rising
RCLK edge, shifts the word from internal memory to the data output lines.


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Texas Instruments
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