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74LVC16374A bảng dữ liệu(PDF) 6 Page - NXP Semiconductors |
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74LVC16374A bảng dữ liệu(HTML) 6 Page - NXP Semiconductors |
6 / 10 page Philips Semiconductors Product specification 74LVC16374A/ 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) 1998 Mar 17 6 DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40 °C to +85°C UNIT MIN TYP1 MAX IBHL Bus hold LOW sustaining current VCC = 3.0V; VI = 0.8V2, 3, 4 75 µA IBHH Bus hold HIGH sustaining current VCC = 3.0V; VI = 2.0V2, 3, 4 –75 µA IBHLO Bus hold LOW overdrive current VCC = 3.6V2, 3, 5 500 µA IBHHO Bus hold HIGH overdrive current VCC = 3.6V2, 3, 5 –500 µA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. Valid for data inputs of bus hold parts (LVCH16-A) only. 3. For data inputs only, control inputs do not have a bus hold circuit. 4. The specified sustaining current at the data input holds the input below the specified VI level. 5. The specified overdrive current at the data input forces the data input to the opposite logic input state. 6. For bus hold parts, the bus hold circuit is switched off when Vi exceeds VCC allowing 5.5V on the input terminal. AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT MIN TYP1 MAX MIN MAX MAX tPHL tPLH Propagation delay CP to Qn 1, 4 1.5 3.8 5.4 1.5 6.4 17 ns tPZH tPZL 3-State output enable time OE to Qn 2, 4 1.5 3.6 5.6 1.5 6.6 20 ns tPHZ tPLZ 3-State output disable time OE to Qn 2, 4 1.5 3.9 5.5 1.5 6.5 12 ns tW CP pulse width HIGH or LOW 1 3.0 1.5 – 3.0 – – ns tsu Set-up time Dn to CP 3 2.0 0.3 – 1.9 – – ns th Hold time Dn to CP 3 1.5 –0.3 – 1.1 – – ns fmax Maximum clock pulse frequency 1 100 – – 80 – – MHz NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. |
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