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74LVC1284PW bảng dữ liệu(PDF) 4 Page - NXP Semiconductors |
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74LVC1284PW bảng dữ liệu(HTML) 4 Page - NXP Semiconductors |
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4 / 10 page  Philips Semiconductors Product specification 74LVC1284 3.3V Parallel printer interface transceiver/buffer 1995 Nov 10 4 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = 25°C Tamb = 0°C to +70°C UNIT MIN TYP MAX MIN MAX High level An VCC = Min to Max; IOH = –50µA VCC–0.2 VCC VCC–0.2 V VOH High-level output voltage An VCC = 3.0V; IOH = –4mA 2.4 2.4 V out ut voltage Bn or Yn VCC = 3.0V; IOH = 14mA 2.2 2.4 2.1 V V Low-level An VCC = Min to Max; IOL = 50µA; VI = VIL or VIH 0.2 0.2 V VOL Low level output voltage VCC = 3.0V; IOL = 4mA; VI = VIL or VIH 0.4 0.4 V Bn or Yn VCC = 3.0V; IOL = –14mA; VI = VIL or VIH 0.8 0.9 V VIH High-level input voltage VCC = Min to Max 0.8 0.8 VIL Low-level input voltage VCC = Min to Max 2.0 2.0 VHYS Input Hysteresis VCC = 3.3V 0.4 0.3 V RD B/Y side Output Impedance See Figure 2 38 45 53 35 55 Ω II Input leakage current (A5-A7 DIR, HD) VCC = 3.6V; VO = VCC or GND; Not for I/O pins ±1.0 ±5.0 µA IIHZ/IILZ Input current for common I/O pins VCC = 3.6V;VI = 5.5V or GND "0.1 "15 µA IOFF B/Y Side Power-off leakage current VCC = 0.0V; VO = 0 to 5.5V ±10 ±100 µA IOZH 3-State output High current Yn VCC = 3.6V; VO = VCC; VI = VIL or VIH 5 20 µA IOZL 3-State output Low current Yn VCC = 3.6V; VO = GND; VI = VIL or VIH –5 –20 µA IIH+IOZH current (A1 – A4, Bn) VCC = 3.6V; VI/O = VCC 5 25 µA IIL+IOZL current (A1 – A4, Bn) VCC = 3.6V; VI/O = GND –5 –25 µA ICC Quiescent Supply Current VCC = 3.6V; IO = 0; VI = GND or VCC 5 10 50 µA AC CHARACTERISTICS GND = 0V, tR = tF = 3.0ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = 25°C VCC = 3.3V Tamb = 0 to + 70°C VCC = Min to Max UNIT MIN TYP MAX MIN MAX SR B-Side Slew Rate 4 0.05 0.2 0.35 0.05 0.4 V/ns tPLH tPHL Propagation delay A toY or A to B 5 6.0 6.0 12.6 12.4 18.0 18.0 5.0 5.0 19.5 20.0 ns tPLH tPHL Propagation delay B to A 1 1.5 1.5 5.5 5.6 7.9 7.6 1.5 1.5 9.5 9.0 ns tPZH tPHZ Output enable/disable time to/from High level HD to Y or HD to B 2 4.0 2.0 12.0 6.5 16.0 9.1 4.0 2.0 20.0 11.0 ns tPZL tPLZ Output enable/disable time to/from Low level A to Y or A to B 2 5.0 1.5 12.7 5.0 16.3 7.1 5.0 1.5 20.0 9.0 ns tPZH tPZL Output enable time from DIR to B 2 8.0 8.0 12.3 12.7 18.0 18.0 4.0 4.0 20.0 20.0 ns tPHZ tPLZ Output disable time from DIR to B 2 5.0 6.0 8.9 9.1 12.5 12.0 2.0 2.0 14.5 14.0 ns tPZH tPZL Output enable time from DIR to A 2 3.5 4.0 6.9 8.6 13.0 14.0 3.0 3.0 14.5 16.0 ns tPHZ tPLZ Output disable from DIR to A 2 2.5 2.5 3.7 3.7 5.5 5.0 2.0 2.0 6.0 5.5 ns |
Số phần tương tự - 74LVC1284PW |
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Mô tả tương tự - 74LVC1284PW |
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