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74LVC02ADB bảng dữ liệu(PDF) 2 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  Quad 2-input NOR gate
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Philips Semiconductors
Product specification
74LVC02A
Quad 2-input NOR gate
2
1998 Apr 28
853-2019 19310
FEATURES
Wide supply range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5V
CMOS low power consumption
Direct interface with TTL levels
5-volt tolerant inputs, for interfacing with 5-volt logic
DESCRIPTION
The 74LVC02A is a high performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature
allows the use of these devices as translators in a mixed 3.3 V/5 V
environment.
The 74LVC02A provides the 2-input NOR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL
tPLH
Propagation delay
nA, nB to nY
CL = 50 pF;
VCC = 3.3 V
2.8
ns
CI
Input capacitance
5.0
pF
CPD
Power dissipation capacitance per gate
Notes 1 and 2
28
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
14-Pin Plastic SO
–40
°C to +85°C
74LVC02A D
74LVC02A D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°C to +85°C
74LVC02A DB
74LVC02A DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°C to +85°C
74LVC02A PW
74LVC02APW DH
SOT402-1
PIN CONFIGURATION
SV00389
1
2
3
4
5
6
7
1Y
1A
1B
2Y
2A
2B
GND
VCC
4Y
4B
4A
3Y
3B
3A
8
9
10
11
12
13
14
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
NAME AND FUNCTION
1, 4, 10, 13
1Y – 4Y
Data outputs
2, 5, 8, 11
1A – 4A
Data inputs
3, 6, 9, 12
1B – 4B
Data inputs
7
GND
Ground (0 V)
14
VCC
Positive supply voltage


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