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74LV393PW bảng dữ liệu(PDF) 7 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV393
Dual 4-bit binary ripple counter
1998 Jun 10
7
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V
VM = 0.5 * VCC at VCC t 2.7V
VOL and VOH are the typical output voltage drop that occur with the
output load.
SV00678
VM
nCP INPUT
VCC
GND
VOH
VOL
nQn OUTPUT
VM
tPLH
tPHL
1/fmax
Figure 1. Clock (nCP) to output (1Qn, 2Qn) propagation delays,
the clock pulse width, and the maximum clock frequency
SV00679
VM
nMR INPUT
nCP INPUT
VCC
VCC
GND
GND
VOL
VOH
nQn OUTPUT
VM
VM
trem
tPHL
tW
Figure 2. Master reset (nMR) pulse width,
the master reset to output (Qn) propagation delays,
and the master reset to clock (nCP) removal time
TEST CIRCUIT
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
RL = 1k
VCC
Test Circuit for switching times
DEFINITIONS
VCC
VI
< 2.7V
VCC
TEST
tPLH/tPHL
RT = Termination resistance should be equal to ZOUT of pulse generators.
50pF
SV00901
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
2.7–3.6V
2.7V
Figure 3. Load circuitry for switching times


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