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ST20GP6X33S bảng dữ liệu(PDF) 10 Page - STMicroelectronics |
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ST20GP6X33S bảng dữ liệu(HTML) 10 Page - STMicroelectronics |
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10 / 123 page  ST20-GP6 10/123 • Power to most of the chip removed — only the real time clock supply ( RTCVDD) power on. In power-down mode the processor and all peripherals are stopped, including the external memory controller and optionally the PLL. Effectively the internal clock is stopped and functional operation is stalled. On restart the clock is restarted and the chip resumes normal functional operation. Serial communications The ST20-GP6 has two UARTs (Asynchronous Serial Controllers (ASCs)) for serial communication. The UARTs provide an asynchronous serial interface and can be programmed to support a range of baud rates and data formats, for example, data size, stop bits and parity. Interrupt subsystem The ST20-GP6 interrupt subsystem supports eight prioritized interrupts. Four interrupts are connected to on-chip peripherals (2 for the UARTs, 2 for the programmable IO), two are available as external interrupt pins and two are spare. Each interrupt level has a higher priority than the previous and each level supports only one software handler process. Note that interrupt handlers must not prevent the GPS DSP data traffic from being handled. During continuous operation this has 1 ms latency and is not a problem, but during initial acquisition it has a 32 µs rate and thus all interrupts must be disabled except if used to stop GPS operation. Parallel IO module Sixteen bits of parallel IO are provided. Each bit is programmable as an output or an input. Edge detection logic is provided which can generate an interrupt on any change of an input bit. JTAG Test Access Port The Test Access Port (TAP) supports the IEEE 1149.1 JTAG test standard. Diagnostic controller The diagnostic controller is a programmable module which connects directly into the CPU. It can be accessed by the TAP. This allows debugging systems to be used which do not affect CPU performance or intrude into application code. Debugging support includes: • hardware breakpoint and watchpoint • real time trace • external LSA triggering support It is also used to provide system services, including booting the CPU. System services module The ST20-GP6 system services module includes: • reset and initialization port. • phase locked loop (PLL) — accepts 16.368 MHz input and generates all the internal high frequency clocks needed for the CPU. |
Số phần tương tự - ST20GP6X33S |
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Mô tả tương tự - ST20GP6X33S |
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