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74LV109PWDH bảng dữ liệu(PDF) 6 Page - NXP Semiconductors |
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74LV109PWDH bảng dữ liệu(HTML) 6 Page - NXP Semiconductors |
6 / 12 page Philips Semiconductors Product specification 74LV109 Dual JK flip-flop with set and reset; positive-edge trigger 1998 Apr 20 6 AC CHARACTERISTICS (Continued) GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ CONDITION LIMITS SYMBOL PARAMETER WAVEFORM CONDITION –40 to +85 °C –40 to +125 °C UNIT VCC(V) MIN TYP1 MAX MIN MAX 1.2 75 tPHL Propagation delay Figure 2 2.0 26 46 60 ns tPHL gy nSD to nQ Figure 2 2.7 19 36 44 ns 3.0 to 3.6 172 29 35 1.2 75 tPHL Propagation delay Figure 2 2.0 26 46 60 ns tPHL gy nRD to nQ Figure 2 2.7 19 36 44 ns 3.0 to 3.6 152 29 35 1.2 70 tPLH Propagation delay Figure 2 2.0 24 44 54 ns tPLH gy nRD to nQ Figure 2 2.7 18 33 40 ns 3.0 to 3.6 132 26 32 Clock pulse width 2.0 34 12 41 tW Clock pulse width HIGH or LOW Figure 1 2.7 25 9 30 ns HIGH or LOW 3.0 to 3.6 20 72 24 Set or reset pulse 2.0 34 9 41 tW Set or reset pulse width HIGH or LOW Figure 2 2.7 25 6 30 ns width HIGH or LOW 3.0 to 3.6 20 52 24 1.2 35 t Removal time Figure 2 2.0 24 12 29 ns trem nSD, nRD to nCP Figure 2 2.7 18 9 21 ns 3.0 to 3.6 14 72 17 1.2 30 t Set-up time Figure 1 2.0 22 10 26 ns tsu nJ, nK to CP Figure 1 2.7 16 8 19 ns 3.0 to 3.6 13 62 15 1.2 –5 th Hold time Figure 1 2.0 5 –2 5 ns th nJ, nK to nCP Figure 1 2.7 5 –1 5 ns 3.0 to 3.6 5 02 5 Maximum clock 2.0 14 40 12 fmax Maximum clock pulse frequency Figure 1 2.7 19 58 16 MHz ulse frequency 3.0 to 3.6 24 702 20 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. |
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