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7 / 40 page 1999 Jan 11 7 Philips Semiconductors Product specification PLL with bandgap controlled VCO 74HCT9046A Phase comparators The signal input (SIGIN) can be directly coupled to the self-biasing amplifier at pin 14, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings. PHASE COMPARATOR 1 (PC1) This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must have a 50% duty factor to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: where: VDEMOUT is the demodulator output at pin 10. VDEMOUT = VPC1OUT (via low-pass). The phase comparator gain is: The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of signals (SIGIN) and the comparator input (COMPIN) as shown in Fig.6. The average of VDEMOUT is equal to 1⁄2VCC when there is no signal or noise at SIGIN and with this input the VCO oscillates at the centre frequency (fc). Typical waveforms for the PC1 loop locked at fc are shown in Fig.7. This figure also shows the actual waveforms across the VCO capacitor at pins 6 and 7 (VC1A and VC1B) to show the relation between these ramps and the VCOOUT voltage. V DEMOUT V CC π ----------- Φ SIGIN Φ COMPIN – () = K p V CC π ----------- Vr ⁄ () = The frequency capture range (2fc) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of the input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration remains locked even with very noisy input signals. Typical behaviour of this type of phase comparator is that it may lock to input frequencies close to the harmonics of the VCO centre frequency. PHASE COMPARATOR 2 (PC2) This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state output stage with sink and source transistors acting as current sources, henceforth called charge pump output of PC2. The circuit functions as an up-down counter (Fig.5) where SIGIN causes an up-count and COMPIN a down count. The current switch charge pump output allows a virtually ideal performance of PC2, due to appliance of some pulse overlap of the up and down signals. See Fig.8a. |
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