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74HCT73 bảng dữ liệu(PDF) 2 Page - NXP Semiconductors |
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74HCT73 bảng dữ liệu(HTML) 2 Page - NXP Semiconductors |
2 / 7 page 9397 750 13815 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 03 — 12 November 2004 2 of 21 Philips Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 3. Quick reference data [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(C L × VCC 2 × f o) = sum of outputs. 4. Ordering information Table 1: Quick reference data GND = 0 V; Tamb =25 °C; tr =tf = 6 ns. Symbol Parameter Conditions Min Typ Max Unit tPHL, tPLH propagation delay CL = 15 pF; VCC =5 V - - nCP to nQ - 16 - ns nCP to nQ - 16 - ns nR to nQ, nQ - 15 - ns fmax maximum clock frequency CL = 15 pF; VCC = 5 V - 77 - MHz CI input capacitance - 3.5 - pF CPD power dissipation capacitance per flip-flop VI = GND to VCC [1] -30 - pF Table 2: Ordering information Type number Package Temperature range Name Description Version 74HC73N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HC73D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC73DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HC73PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 |
Số phần tương tự - 74HCT73 |
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Mô tả tương tự - 74HCT73 |
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