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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet

Rev. 03 — 12 November 2004

5 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

7.

Functional description

7.1 Function table

[1]

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;

L = LOW voltage level;

I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;

q = state of referenced output one set-up time prior to the HIGH-to-LOW CP transition;

X = don’t care;

↓ = HIGH-to-LOW CP transition.

8.

Limiting values

[1]

Above 70

[2]

Above 70

GND

11

ground (0 V)

1Q

12

true flip-flop 1 output

1Q

13

complement flip-flop 1 output

1J

14

synchronous J input for flip-flop 1

Table 3:

Symbol

Pin

Description

Table 4:

Function table [1]

Input

Output

Operating mode

nR

nCP

nJ

nK

nQ

nQ

L

X

X

X

L

H

asynchronous reset

H

↓

hh

q

q

toggle

l

h

L

H

load 0 (reset)

h

l

H

L

load 1 (set)

llq

q

hold (no change)

Table 5:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

−0.5 +7

V

input diode current

-

±20

mA

output diode current

-

±20

mA

output source or sink

current

-

±25

mA

-

±50

mA

storage temperature

−65

+150

°C

power dissipation

DIP14 package

[1] -

750

mW

SO14, SSOP14 and

TSSOP14 packages

[2] -

500

mW