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74HCT670D bảng dữ liệu(PDF) 3 Page - NXP Semiconductors

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December 1990
3
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
74HC/HCT670
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
5, 4
RA, RB
read address inputs
8
GND
ground (0 V)
10, 9, 7, 6
Q0 to Q3
data outputs
11
RE
3-state output read enable input (active LOW)
12
WE
write enable input (active LOW)
14, 13
WA, WB
write address inputs
15, 1, 2, 3
D0 to D3
data inputs
16
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
WRITE MODE SELECT TABLE
Note
1. The write address (WA and WB) to the
“internal latches” must be stable while WE is
LOW for conventional operation.
OPERATING
MODE
INPUTS
INTERNAL
LATCHES(1)
WE
Dn
write data
L
L
L
H
L
H
data latched
H
X
no change
READ MODE SELECT TABLE
Notes
1. The selection of the “internal latches” by read address
(RA and RB) are not constrained by WE or RE operation.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
OPERATING
MODE
INPUTS
OUTPUT
RE
INTERNAL LATCHES(1)
Qn
read
L
L
L
H
L
H
disabled
H
X
Z


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