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74HCT594D bảng dữ liệu(PDF) 8 Page - NXP Semiconductors |
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74HCT594D bảng dữ liệu(HTML) 8 Page - NXP Semiconductors |
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8 / 10 page  December 1991 8 Philips Semiconductors Product specification 8-bit shift register with output register 74HC/HCT594 DC CHARACTERISTICS FOR 74HCT For the DC characteristics, see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver; serial output, standard. ICC category: MSI. Note to HCT types The value of additional quiescent supply current ( ∆I CC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the following table. INPUT UNIT LOAD COEFFICIENT Ds 0.25 SHR 1.50 SHCP 1.50 STCP 1.50 STR 1.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS +25 −40 to +85 −40 to +125 VCC (V) WAVEFORMS min. typ. max. min. max. min. max. tPHL/tPLH propagation delay SHCP to Q7’ − 18 32 − 40 − 48 ns 4.5 Fig.7 propagation delay STCP to Qn − 18 32 − 40 − 48 ns 4.5 Fig.8 tPHL propagation delay SHR to Q7’ − 17 30 − 38 − 45 ns 4.5 Fig.11 propagation delay STR to Qn − 17 30 − 38 − 45 ns 4.5 Fig.12 tW shift clock pulse width HIGH or LOW 16 4 − 20 − 24 − ns 4.5 Fig.7 storage clock pulse width HIGH or LOW 16 4 − 20 − 24 − ns 4.5 Fig.8 shift and storage reset pulse width HIGH or LOW 16 6 − 20 − 24 − ns 4.5 Fig.11 and Fig.12 tsu set-up time Ds to SHCP 20 4 − 25 − 30 − ns 4.5 Fig.9 set-up time SHR to STCP 20 6 − 25 − 30 − ns 4.5 Fig.10 set-up time SHCP to STCP 20 7 − 25 − 30 − ns 4.5 Fig.8 th hold time Ds to SHCP 5 −3 − 6 − 7 − ns 4.5 Fig.9 trem removal time SHR to SHCP, STR to STCP 10 −5 − 13 − 15 − ns 4.5 Fig.11 and Fig.12 fmax maximum clock frequency SHCP or STCP 30 92 − 24 − 20 − MHz 4.5 Fig.7 and Fig.8 |
Số phần tương tự - 74HCT594D |
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Mô tả tương tự - 74HCT594D |
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