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74HCT533 bảng dữ liệu(PDF) 2 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  Octal D-type transparent latch; 3-state; inverting
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December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT533
FEATURES
• 3-state inverting outputs for bus oriented applications
• Common 3-state output enable input
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT533 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT533 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
latches.
The “533” consists of eight D-type transparent latches with
3-state inverting outputs. When LE is HIGH, data at the Dn
inputs enter the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the 8 latches are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The “533” is functionally identical to the “373”, “563” and
“573”, but the “373” and “573” have non-inverted outputs
and the “563” and “573” have a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC =5 V
Dn to Qn
14
16
ns
LE to Qn
18
19
ns
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation capacitance per latch
notes 1 and 2
34
34
pF


Số phần tương tự - 74HCT533

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Mô tả tương tự - 74HCT533

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