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74HCT42PW bảng dữ liệu(PDF) 2 Page - NXP Semiconductors |
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74HCT42PW bảng dữ liệu(HTML) 2 Page - NXP Semiconductors |
2 / 6 page December 1990 2 Philips Semiconductors Product specification BCD to decimal decoder (1-of-10) 74HC/HCT42 FEATURES • Mutually exclusive outputs • 1-of-8 demultiplexing capability • Outputs disabled for input codes above nine • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT42 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT42 decoders accept four active HIGH BCD inputs and provide 10 mutually exclusive active LOW outputs. The active LOW outputs facilitate addressing other MSI circuits with active LOW input enables. The logic design of the “42” ensures that all outputs are HIGH when binary codes greater than nine are applied to the inputs. The most significant input (A3) produces an useful inhibit function when the “42” is used as a 1-of-8 decoder. The A3 input can also be used as the data input in an 8-output demultiplexer application. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay An to Yn CL = 15 pF; VCC = 5 V 14 17 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 37 37 pF |
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