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WV3HG64M72AER403AD6SG bảng dữ liệu(PDF) 6 Page - White Electronic Designs Corporation |
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WV3HG64M72AER403AD6SG bảng dữ liệu(HTML) 6 Page - White Electronic Designs Corporation |
6 / 10 page WV3HG64M72AER-AD6 March 2005 Rev. 1 ADVANCED 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC TIMING PARAMETERS 0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V AC CHARACTERISTICS 534 403 PARAMETER SYMBOL MIN MAX MIN MAX UNIT Clock cycle time CL = 4 tCK (4) 3,750 8,000 5,000 8,000 ps CL = 3 tCK (3) 5,000 8,000 5,000 8,000 ps CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK Half clock period tHP MIN (tCH, tCL) MIN (tCH, tCL)ps DQ output access time from CK/CK# tAC -500 +500 -600 +600 ps Data-out high-impedance window from CK/CK# tHZ tAC MAX tAC MAX ps Data-out low-impedance window from CK/CK# tLZ tAC MIN tAC MAX tAC MIN tAC MAX ps DQ and DM input setup time relative to DQS tDS 100 150 ps DQ and DM input hold time relative to DQS tDH 225 275 ps A DQ and DM input pulse width (for each input) tDIPW 0.35 0.35 tCK Data hold skew factor tQHS 400 450 ps DQ…DQS hold, DQS to first DQ to go nonvalid, per access tQH tHP - tQHS tHP - tQHS ps DQS input high pulse width tDQSH 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 tCK DQS output access time from CK/CK# tDQSCK -450 +450 -500 +500 ps DQS falling edge to CK rising … setup time tDSS 0.2 0.2 tCK DQS falling edge from CK rising … hold time tDSH 0.2 0.2 tCK DQS…DQ skew, DQS to last DQ valid, per group, per access tDQSQ 300 350 ps DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK DQS write preamble tWPRE 0.35 0.35 tCK DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK Continued on next page |
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Mô tả tương tự - WV3HG64M72AER403AD6SG |
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