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STK672-330 bảng dữ liệu(PDF) 6 Page - Sanyo Semicon Device |
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STK672-330 bảng dữ liệu(HTML) 6 Page - Sanyo Semicon Device |
6 / 11 page No. 7304-6/11 STK672-330 Note: In the STK672-350 and 360, the RESETB signal must be input at least 10 µs after the rise of the motor power supply VCC level (10 V, minimum), not after the rise of the 5 V power supply (4.5 V, minimum). CLOCK (Phase switching clock) • Input frequency: DC to 50 kHz • Minimum pulse width: 10 µs • Signals are read on the rising edge. CWB (Motor direction setting) The direction of rotation is switched by setting CWB to 1 (high) or 0 (low). See the timing charts for details on the operation of the outputs. Note: The state of the CWB input must not be changed during the 6.25 µs period before and after the rising edge of the CLOCK input. ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and selection of the operate or hold state for hybrid IC internal operation) ENABLE = 1 (high): Normal operation ENABLE = 0 (low): Outputs A, AB, B, and BB forced to the off state. If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 (low) and then is later restored to the 1 (high) state, the IC will resume operation with the excitation timing continued from before the point ENABLE was set to 0 (low). MODE (Excitation mode selection) MODE = 0 (low): 2-phase excitation MODE = 1 (high): 1-2 phase excitation See the timing charts for details on output operation in these modes. Note: The state of the MODE input must not be changed during the 5 µs period before and after the rising edge of the CLOCK input. • Allowable motor current operating range The motor current (IO) must be held within the range corresponding to the area under the curve shown in figure 3. For example, if the operating substrate temperature Tc is 105°C, then IO must be held under IO max = 1.8 A, and in hold mode IO must be held under IO max = 1.5 A. |
Số phần tương tự - STK672-330 |
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Mô tả tương tự - STK672-330 |
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