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STRT71XF bảng dữ liệu(PDF) 5 Page - STMicroelectronics |
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STRT71XF bảng dữ liệu(HTML) 5 Page - STMicroelectronics |
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5 / 74 page  STR71xF Introduction 5/74 The three 64-pin versions (BGA or LQFP) do not include External Memory Interface. ● STR715F: 64-pin BGA or LQFP without CAN or USB ● STR711F: 64-pin BGA or LQFP with USB ● STR712F: 64-pin BGA or LQFP with CAN High Speed Flash Memory (STR71xF) The Flash program memory is organized in two banks of 32-bit wide Burst Flash memories enabling true read-while-write (RWW) operation. Device Bank 0 is up to 256 Kbytes in size, typically for the application program code. Bank 1 is 16K bytes, typically used for storing data constants. Both banks are accessed by the CPU with zero wait states @ 33 MHz Bank 0 memory endurance is 10K write/erase cycles and Bank 1 endurance is 100K write/erase cycles. Data retention is 20 years on both banks. The two banks can be accessed independently in read or write. Flash memory can be accessed in two modes: ● Burst mode: 64-bit wide memory access at up to 50 MHz. ● Direct 32-bit wide memory access for deterministic operation at up to 33 MHz. The STR7 embedded Flash memory can be programmed using In-Circuit Programming or In-Application programming. IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board. The Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection: ● Sector Write Protection ● Flash Debug Protection (locks JTAG access) Refer to the STR7 Flash Programming Reference manual for details. Optional External Memory (STR710) The non-multiplexed 16-bit data/24-bit address bus available on the STR710 (144-pin) supports four 16-Mbyte banks of external memory. Wait states are programmable individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM etc.) to be used to store programs or data. Figure 1 shows the general block diagram of the device family. Flexible Power Management To minimize power consumption, you can program the STR710 to switch to SLOW, WAIT, LPWAIT (low power wait), STOP or STANDBY mode depending on the current system activity in the application. Flexible Clock Control Two external clock sources can be used, a main clock and a 32 kHz backup clock. The embedded PLL allows the internal system clock (up to 66 MHz) to be generated from a main clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. The microcontroller core, APB1 and APB2 peripherals are in separate clock domains and can be programmed to run at different frequencies during application runtime. The clock to each peripheral is gated with an |
Số phần tương tự - STRT71XF |
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Mô tả tương tự - STRT71XF |
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