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MC14LC5480SD bảng dữ liệu(PDF) 4 Page - Freescale Semiconductor, Inc |
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4 / 24 page therefore low impedance loads must be between PO+ and PO–. Connecting PI to VDD will power down the power driver amplifiers and the PO+ and PO– outputs will be high imped- ance. This pin is also high impedance when the device is powered down by the PDI pin. PO+ Power Amplifier Output (Non–Inverting) (Pin 5) This is the non–inverting power amplifier output, which is an inverted version of the signal at PO–. This pin is capable of driving a 300 Ω load to PO–. Connecting PI to VDD will power down the power driver amplifiers and the PO+ and PO– outputs will be high impedance. This pin is also high im- pedance when the device is powered down by the PDI pin. See PI and PO– for more information. DIGITAL INTERFACE MCLK Master Clock (Pin 11) This is the master clock input pin. The clock signal applied to this pin is used to generate the internal 256 kHz clock and sequencing signals for the switched–capacitor filters, ADC, and DAC. The internal prescaler logic compares the clock on this pin to the clock at FST (8 kHz) and will automatically accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For MCLK frequencies of 256 and 512 kHz, MCLK must be syn- chronous and approximately rising edge aligned to FST. For optimum performance at frequencies of 1.536 MHz and higher, MCLK should be synchronous and approximately ris- ing edge aligned to the rising edge of FST. In many ap- plications, MCLK may be tied to the BCLKT pin. FST Frame Sync, Transmit (Pin 14) This pin accepts an 8 kHz clock that synchronizes the out- put of the serial PCM data at the DT pin. This input is com- patible with various standards including IDL, Long Frame Sync, Short Frame Sync, and GCI formats. If both FST and FSR are held low for several 8 kHz frames, the device will power down. BCLKT Bit Clock, Transmit (Pin 12) This pin controls the transfer rate of transmit PCM data. In the IDL and GCI modes it also controls the transfer rate of the receive PCM data. This pin can accept any bit clock fre- quency from 64 to 4096 kHz for Long Frame Sync and Short Frame Sync timing. This pin can accept clock frequencies from 256 kHz to 4.096 MHz in IDL mode, and from 512 kHz to 6.176 MHz for GCI timing mode. DT Data, Transmit (Pin 13) This pin is controlled by FST and BCLKT and is high im- pedance except when outputting PCM data. When operating in the IDL or GCI mode, data is output in either the B1 or B2 channel as selected by FSR. This pin is high impedance when the device is in the powered down mode. FSR Frame Sync, Receive (Pin 7) When used in the Long Frame Sync or Short Frame Sync mode, this pin accepts an 8 kHz clock, which synchronizes the input of the serial PCM data at the DR pin. FSR can be asynchronous to FST in the Long Frame Sync or Short Frame Sync modes. When an ISDN mode (IDL or GCI) has been selected with BCLKR, this pin selects either B1 (logic 0) or B2 (logic 1) as the active data channel. BCLKR Bit Clock, Receive (Pin 9) When used in the Long Frame Sync or Short Frame Sync mode, this pin accepts any bit clock frequency from 64 to 4096 kHz. When this pin is held at a logic 1, FST, BCLKT, DT, and DR become IDL Interface compatible. When this pin is held at a logic 0, FST, BCLKT, DT, and DR become GCI Inter- face compatible. DR Data, Receive (Pin 8) This pin is the PCM data input, and when in a Long Frame Sync or Short Frame Sync mode is controlled by FSR and BCLKR. When in the IDL or GCI mode, this data transfer is controlled by FST and BCLKT. FSR and BCLKR select the B channel and ISDN mode, respectively. FUNCTIONAL DESCRIPTION ANALOG INTERFACE AND SIGNAL PATH The transmit portion of this device includes a low–noise, three–terminal op amp capable of driving a 2 k Ω load. This op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its output is TG (Pin 17). This op amp is intended to be confi- gured in an inverting gain circuit. The analog signal may be applied directly to the TG pin if this transmit op amp is inde- pendently powered down by connecting the TI+ and TI– inputs to the VDD power supply. The TG pin becomes high impedance when the transmit op amp is powered down. The TG pin is internally connected to a 3–pole anti–aliasing pre– filter. This pre–filter incorporates a 2–pole Butterworth active low–pass filter, followed by a single passive pole. This pre– filter is followed by a single–ended to differential converter that is clocked at 512 kHz. All subsequent analog processing utilizes fully–differential circuitry. The next section is a fully– differential, 5–pole switched–capacitor low–pass filter with a 3.4 kHz frequency cutoff. After this filter is a 3–pole switched–capacitor high–pass filter having a cutoff fre- quency of about 200 Hz. This high–pass stage has a trans- mission zero at dc that eliminates any dc coming from the analog input or from accumulated op amp offsets in the pre- ceding filter stages. The last stage of the high–pass filter is an autozeroed sample and hold amplifier. One bandgap voltage reference generator and digital–to– analog converter (DAC) are shared by the transmit and re- ceive sections. The autozeroed, switched–capacitor bandgap reference generates precise positive and negative reference voltages that are virtually independent of tempera- ture and power supply voltage. A binary–weighted capacitor array (CDAC) forms the chords of the companding structure, while a resistor string (RDAC) implements the linear steps within each chord. The encode process uses the DAC, the voltage reference, and a frame–by–frame autozeroed comparator to implement a successive–approximation con- Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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