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74F191 bảng dữ liệu(PDF) 5 Page - NXP Semiconductors |
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74F191 bảng dữ liệu(HTML) 5 Page - NXP Semiconductors |
5 / 14 page Philips Semiconductors Product specification 74F191 Up/Down binary counter with reset and ripple clock 1995 Jul 17 5 APPLICATIONS U/D CE CP U/D CE CP U/D CE CP U/D CE CP U/D CE CP U/D CE CP U/D CE CP U/D CE CP U/D CE CP TC TC TC RC RC RC RC RC RC DIRECTION CONTROL CLOCK ENABLE ENABLE DIRECTION CONTROL CLOCK ENABLE DIRECTION CONTROL CLOCK a. N-Stage Counter Using Ripple Clock b. Synchronous N-Stage Counter with Common Clock Using Ripple/Clock c. Synchronous N-Stage Counter with Common Clock and Terminal Count * = Carry Gate ** SF00733 Figure 1. The 74F191 simplifies the design of multi-stage counters, as indicated in Figure 1, each RC output is used as the clock input for the next higher stage. When the clock source has a limited drive capability this configuration is particularly advantageous, since the clock source drives only the first stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a High signal on CE inhibits the RC output pulse as indicated in the Mode Select Table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This is a disadvantage of the configuration in some applications. Figure 1b shows a method of causing state changes to occur simultaneously in all stages. The RC output signals propagate in ripple fashion and all clock inputs are driven in parallel. The Low state duration of the clock in this configuration must be long enough to allow the negative-going edge of the RC signal to ripple through to the last stage before the clock goes High. Since the RC output of any package goes High shortly after its clock input goes High, there is no such restriction on the High state duration of the clock. In Figure 1c, the configuration shown avoids ripple delays and their associated restrictions. The combined TC signals from all the preceding stages forms the CE input signal for a given stage. An enable signal must also be included in each carry gate in order to inhibit counting. The TC output of a given stage is not affected by its own CE, therefore, the simple inhibit scheme of Figure 1a and 1b does not apply. |
Số phần tương tự - 74F191 |
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Mô tả tương tự - 74F191 |
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